UltraSparc I: a four-issue processor supporting multimedia

A non-destructive testing method using ultrasonic waves for composite materials has been studied. In this paper, a computer program of three dimensional image processing was developed to evaluate the defects in composite materials. The developed computer program has two particular functions, which are smoothing of scan data and decision of defect size. The size of defect was obtained by a gradient of echo level. As the examples, this method was applied to GFRP and CFRP laminates with artificial defects, and the effect of processing on the size of defects was investigated. As a result, the shape, size and location of defects in composite materials were obtained by the three dimensional image processing. It is also revealed that the detectability of defects is improved by this method. From these results, it can be shown that the method proposed in this paper is very useful to evaluate defects in composite materials.

This paper describes our new method of automatic interpretation of cross sectional pictures of human body. In our case, 2-dimensional image of liver is extracted from abdominal MR images. And by reconstructing 3-dimensional (3-D) images, we had volumetric estimation. Fuzzy inference was utilized in extraction processing, so that our processing system could involve logic of image interpretation. Resulting volumetric measurement of our 3-dimensional estimation was underestimation by some 11%, when compared to that of a human expert's estimation. Our processing method is valid for segmentation of soft tissue, which is hard to be processed by only conventional image processing. And this method will lead to real time 3- dimensional image processing in the future.

The Multi-Level Computing Architecture (MLCA) is a novel parallel System-on-a-Chip architecture targeted for multimedia applications. It features a top level controller that automatically extracts task level parallelism using techniques similar to how instruction level parallelism is extracted by superscalar processors. This allows the MLCA to support a simple programming model that is similar to sequential programming. In order to assist programmers to easily and efficiently port multimedia applications to the MLCA programming model, a compilation environment is designed. This compilation environment enhances parallelism in MLCA programs by applying three simple code transformations that are based on known compiler optimizations. In this paper, we describe the MLCA architecture, its programming model, its compilation environment and an evaluation of its performance. Our experimental evaluation with three real multimedia applications and an MLCA simulator shows that the MLCA is a viable architecture and scaling speedups can be obtained using the compilation environment with little programmer effort.

Segmentation of targets from a set of disordered objects is always plays a significant role in the field of computer vision. In this paper, a novel method of object segmentation of scattered parts, of which dense and accurate 3D point cloud can be obtained by visual measurement technology of the structured light, is proposed and confirmed to be valid without training large datasets. The randomly placed parts are almost separated completely after two dimensional image processing and point cloud segmentation using local convex convexity connections. The segmentation results can guide the grabbing work of robot arms in the bin-picking system.

We consider the problem of minimizing the continuous valued total variation subject to different unary terms on trees and propose fast direct algorithms based on dynamic programming to solve these problems. We treat both the convex and the non-convex case and derive worst case complexities that are equal or better than existing methods. We show applications to total variation based 2D image processing and computer vision problems based on a Lagrangian decomposition approach. The resulting algorithms are very efficient, offer a high degree of parallelism and come along with memory requirements which are only in the order of the number of image pixels.

医療における三次元画像処理の応用

High performance processors based on pipeline processing play an important role in scientific computation. We have proposed a hybrid pipeline architecture named Jetpipeline in our former work. The concept of Jetpipeline comes from the integration of superscalar, VLIW and vector architectures. Jetpipeline has multiple instruction pipelines, which execute multiple instructions like superscalar architectures. Instructions to be executed simultaneously are statically scheduled by a compiler like VLIW architectures. Therefore, parallelism derivation and instruction scheduling are very important for Jetpipeline. Software pipelining is one of the well-known techniques to achieve high throughput when processing loop programs. In this paper, we propose software pipelining for Jetpipeline. Firstly, the overview of the Jetpipeline architecture is described. Then the banked register configuration of Jetpipeline for reducing hardware complexity and supporting software pipelining is presented. Finally, the effectiveness of software pipelining for Jetpipeline is discussed by simulation. >

Real-time 3D graphics will be a major power consumer in future portable embedded systems. 3D graphics is characterized by intensive floating point calculations, heavy data traffic between memory and peripherals, and a high degree of non-uniformity due to content variation. Although 3D graphics is currently very limited in power-constrained environments, future user interfaces (head-mounted virtual reality) and applications (simulators, collaboration environments, etc.) will require power-aware implementations. Fortunately, we can exploit content variation and human perception to significantly reduce the power consumption of many aspects of 3D graphic rendering. In this paper we study the impact on power consumption of novel adaptive shading algorithms (both Gouraud and Phong) which consider both the graphics content (e.g. motion, scene change) and the perception of the user. Novel dynamically configurable architectures are proposed to efficiently implement the adaptive algorithms in power-aware systems with gracefully degradable quality. This paper introduces an integrated algorithm and hardware solution based on human visual perceptual characteristics and dynamically re-configurable hardware. Three approaches are explored which are both based on human vision and loosely analogous to video coding techniques. The first approach is called distributed computation over frames and exploits the after image phenomenon of the human visual system. The second approach exploits visual sensitivity to motion. According to the speed and distance from camera to object, either the Gouraud or Phong shading algorithm is selected. The third approach is an adaptive computation of the specular term computation used in Phong. Using the same selection criteria as in adaptive shading, a reduced computational cost algorithm is used for fast moving objects. Results based on simulation indicate a power savings of up to 85% using short but realistic rendering sequences. Future work includes: 1) more sophisticated architectures to support dynamic reconfiguration, 2)exploring other steps in the 3D graphics pipeline, and 3) extending these ideas to other multimedia applications which involve variable content, computation and human perception (for example, video and audio coding).

Application-specific extensions of a processor provide an efficient mechanism that meets the growing performance and power demands of portable embedded applications such as interactive multimedia communications. This work investigates the use of both the luminance and chrominance components in color image- and video-processing applications and proposes a color-aware instruction set extension (CAX) that improves the performance of color multimedia-processing applications. The CAX ISA is able to exploit a new level of subword parallelism not reachable by current multimedia extensions. Unlike typical multimedia extensions (e.g., Intel MMX, MIPS MDMX, and AMD 3DNow!), CAX instructions support parallel operations on two-packed 16-bit (6:5:5) YCbCr color pixels in a 32-bit datapath width and obtain substantial performance and code density improvements through direct support for color data processing rather than depending solely on generic subword parallelism. The results on a set of media benchmark applications indicate that the CAX versions achieve a speedup ranging from 3x to 5.8x while reducing energy consumption from 68% to 83% over the baseline versions on an identically-configured, dynamically-scheduled superscalar processor. The CAX versions also outperform the MDMX (MIPS multimedia extension) performance.

This report describes a preoperative simulation and intraoperative localization system for use with three-dimensional functional images in intracranial surgery. The system, which produces three-dimensional functional images by superimposition of the generators of somatosensory evoked potentials derived from dipole tracing, was applied in the preoperative localization of central sulci in 12 patients with intracranial disorders. The preoperative localization of central sulci was assessed by intraoperative cortical recording of somatosensory evoked potentials in three patients. In six patients, three-dimensional computer graphics were reconstructed from magnetic resonance images and allowed visualization of the lesions through the semitransparent views of the scalp surface and the brain. The three-dimensional functional images were created by superimposing the generators of somatosensory evoked potentials on three-dimensional computer graphics. This combined technique provided preoperative data regarding the three-dimensional relationship between the sensorimotor cortex and the lesions. We also developed a three-dimensional digitizer that incorporates a mechanical arm and a laser pointer for use in integrating information obtained in the preoperative simulation into the surgical field. Intraoperative localization can be performed in real time on the three-dimensional computer graphics in combination with the functional images created from dipole tracing. This system was applied in five patients who underwent surgical brain tumor resections with minimal damage to the normal brain tissue. The use of this system for stereotactic craniotomy increased the safety of the surgery by affording preoperative simulation and intraoperative localization with the three-dimensional functional images. Two illustrative case reports are presented.

In order to overcome the seriously constrained storage and processing problem of a single node in wireless multimedia sensor networks (WMSNs), based on the study of LBT,LBT based the distributed image compression algorithm is proposed for wireless multimedia sensor networks. Namely, adopt low-complexity, high compression efficiency LBT image compression algorithm, through multiple relay nodes collaborating, together to accomplish the image compression coding and forwarding. Simulation results show that the algorithm has extremely high network performance with low memory and processing requirements.

For performance enhancement, reconfigurable processors have to overcome the overheads of reconfigurations such as the complexity of the interconnection network and reconfiguration time. In processors dealing with multimedia applications these overheads can be reduced by providing the reconfigurability inside the processing units rather than at interconnection level. Due to the low precision data nature of multimedia applications, reconfiguration at operator level also provides additional speedup through parallel execution of low precision data. In this paper a pipelined architecture of a reconfigurable coarse grain subword parallel (SWP) operator is presented for multimedia applications. This operator not only eliminates the need of reconfiguration time but also provides the reconfigurability at both data size level (different pixel data sizes) and at operation level (different multimedia oriented operations). This ensures a better utilization of the processor resources and reduces the reconfiguration overheads significantly.

Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geometry processing of 3D graphics on the host CPU and have specialized hardware handle the rendering task. In this paper, we analyze microarchitecture and SIMD instruction set enhancements to a RISC superscalar processor for exploiting instruction level parallelism (ILP) in geometry processing for 3D computer graphics. Our results show that 3D geometry processing has inherent parallelism. When ignoring cycle time effects, an 8-issue processor can achieve up to 60% performance improvement over a 4-issue. However, certain application attributes can hinder the exploitation of ILP on a superscalar processor. Adding SIMD operations improves performance from 8% to 28% on a 4-issue processor that can issue at most 2 floating-point operations. If processor cycle time scales with the number of ports to the register file, doubling only the floating-point issue width of a 4-issue processor with SIMD instructions gives the best performance among the architecture configurations that we examine (the most aggressive configuration is an 8-issue processor with SIMD instructions).

Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geometry processing of 3D graphics on the host CPU and have specialized hardware handle the rendering task. In this paper, we analyze microarchitecture and SIMD instruction set enhancements to a RISC superscalar processor for exploiting instruction level parallelism (ILP) in geometry processing for 3D computer graphics. Our results show that 3D geometry processing has inherent parallelism. When ignoring cycle time effects, an 8-issue processor can achieve up to 60% performance improvement over a 4-issue. However, certain application attributes can hinder the exploitation of ILP on a superscalar processor. Adding SIMD operations improves performance from 8% to 28% on a 4-issue processor that can issue at most 2 floating-point operations. If processor cycle time scales with the number of ports to the register file, doubling only the floating-point issue width of a 4-issue processor with SIMD instructions gives the best performance among the architecture configurations that we examine (the most aggressive configuration is an 8-issue processor with SIMD instructions).

We explore the design, implementation, and evaluation of a coarse-grain superscalar processor in the context of the microarchitecture of the Control Processor (CP) of the Multilevel Computing Architecture (MLCA), a novel architecture targeted for multimedia multicore systems. The MLCA augments a traditional multicore architecture (called the lower level) with a CP (called the top-level), which automatically extracts parallelism among coarse-grain units of computation (tasks), synchronizes these tasks and schedules them for execution on processors. It does so in a fashion similar to how instruction-level parallelism is extracted by superscalar processors, i.e., using register renaming, Out-of-Order Execution (OoOE) and scheduling. The coarse-grain nature of tasks imposes challenging constraints on the direct use of these techniques, but also offers opportunities for simpler designs. We analyze the impact of these constraints and opportunities and present novel microarchitectural mechanisms for coarse-grain superscalar execution, including register renaming, task queue, dynamic out-of-order scheduling and task-issue. We design an MLCA system around our CP microarchitecture and implement it on an FPGA. We evaluate the system using multimedia applications and show good scalability for eight processors, limited by the memory bandwidth of the FPGA platform. Furthermore, we show that the CP introduces little overhead in terms of resource usage. Finally, we show scalability beyond eight processors using cycle-accurate RTL-level simulation with an idealized memory subsystem. We demonstrate that the CP poses no performance bottlenecks and is scalable up to 32 processors.