31- https://doi.org/10.1145/73141.74849
Unified management of registers and cache using liveness and cache bypass
- Jun 21, 1989
- C.-H Chi +1 more
Abstract
In current computer memory system hierarchy, registers and cache are both used to bridge the reference delay gap between the fast processor(s) and the slow main memory. While registers are managed by the compiler using program flow analysis, cache is mainly controlled by hardware without any program understanding. Due to the lack of coordination in managing these two memory structures, significant loss of system performance results because:
- # Slow Main Memory
- # Program Flow Analysis
- # Cache Bypass
- # Program Understanding
- # Memory Structures
- # Fast Processor
- # Management Of Cache
- # Slow Memory
- # Current Memory
- # Memory Registers
