Unique method to electrically characterize a single stacking fault in silicon-on-insulator metal–oxide–semiconductor field-effect transistors

The influence of gamma-radiation on the electrical characteristics of 6H–SiC p-channel metal–oxide–semiconductor field effect transistors (MOSFETs) containing step bunching is reported. The formation of step bunching perpendicular to the channel inhibited the current flow, whereas such an effect was not seen in devices with step bunching formed parallel to the channel. The effective channel mobility in the latter devices increases with gamma-radiation. This improvement of the hole mobility is attributed partially to the positively trapped charges screened the holes from approaching too close to the surface and partially to the effect of position of these charges, resulting in a reduction of scattering and capture of holes. No enhancement in the effective channel mobility was observed for devices with no step bunching or with root mean square roughness in the channel region less than 4 nm. Further irradiation leads to a decrease in the effective channel mobility due to both the formation of latent interface traps and electrostatics repulsion of holes.

The optimization of the noise performance of integrated complementary metal-oxide semiconductor (CMOS) charge amplifiers is studied in detail considering accurate 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> noise modeling for the input metal-oxide semiconductor field-effect transistor (MOSFET) biased in a strong inversion-saturation region. This paper aims to generalize and correct previously published analyses which have been based on two limiting and sometimes not applicable assumptions: a fixed MOSFETs bias current and the general validity of the McWhorter 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> noise model. This study considers the two main 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> noise models: (1) the mobility fluctuation, known as Deltamu or Hooge model, which is followed by p-channel MOSFETs and (2) the carriers number fluctuation, also known as DeltaN or McWhorter model, which is applicable only for n-channel MOSFETs. The front-end noise optimization is made with the 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> component alone, thus determining the ultimate performance, and also considering the presence of series and parallel white noise sources. It is shown that different design criteria are valid of p- or n-channel MOSFETs: the Deltamu model results in an optimum bias current and a different optimum gate width with respect to DeltaN model. Two-dimensions suboptimum noise minimization criteria are derived when power or area constraints are imposed to the circuit design. Starting from experimental data on CMOS 1/f noise, examples of application of the presented analysis are shown to predict the lower limits of the 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> noise contribution for the currently available CMOS technologies.

The temperature and drain current (ID) dependencies of sub-threshold swing (SS) values of Si n- and p-channel metal–oxide–semiconductor field effect transistors (MOSFETs) with different substrate impurity concentrations ranging from the 1015 to 1018 cm−3 ranges are systematically and experimentally evaluated at cryogenic temperatures. It is found that SS of p-channel MOSFETs tends to increase with decreasing temperature, which contrasts with saturation of SS of n-MOSFETs at cryogenic temperatures, well reported by many previous works. To explain these SS behaviors quantitatively, we employ a density-of-state (DOS) model with tail states consisting of localized states in a deep energy range and mobile states in a shallow energy range, which are attributable to potential fluctuations caused by substrate impurities. It is shown that this model can quantitatively explain the temperature and ID dependencies of SS of both n-MOSFETs and p-MOSFETs. Then, we are assuming that the Si p-MOSFET has a higher density of localized states than the n-MOSFET. Thus, the increase in SS of the p-MOSFETs with decreasing temperature is explained by an increase in the density of localized states at the Fermi level with decreasing temperature, because the density of localized states increases with elevating the Fermi level position in the employed DOS model.

Detection of ESD-induced noncatastrophic damage in p-channel power MOSFETs

Selective buried oxide (SELBOX) Metal‐Oxide‐Semiconductor Field‐Effect Transistor (MOSFET) structure can be used to reduce the kink effect and self‐heating problems associated with the silicon on insulator (SOI) MOSFET devices while maintaining the advantages of bulk MOSFET. In this paper, static power dissipation of SELBOX structure is investigated and compared with SOI and bulk structures. Various MOSFET structures are simulated and evaluated in terms of their static power dissipation. Only results from 90‐nm Complementary Metal Oxide Semiconductor (CMOS) technology devices are included in this paper. Simulation results using the Silvaco TCAD show that static power dissipation in SELBOX CMOS is similar to that of SOI devices but lower than that of bulk CMOS. Hence, SELBOX structure is found to produce relatively low‐static power dissipation while maintaining high operating speed and reducing self‐heating and kink effect. A mathematical model to describe the static power dissipation in the subthreshold region is also included. Statistical analysis show that the model and fabrication simulation results agree with P &lt; .05 and correlation coefficient of 0.95.

Novel metal oxide semiconductor field effect transistor (MOSFET) architectures aimed at sub 1 V operation with enhanced current driving capability are reported. In our design, the planar channel region in a conventional MOSFET is replaced by an array of isolated Si wires. Directional metal coverage of the two sidewalls and the top surface of each Si wire help achieve enhanced gate control. Sub 1 V operation is achieved by reducing cross-sectional wire diameters to /spl sim/0.05 /spl mu/m. Since the conventional optical lithography techniques lack patterning resolution at this scale, a mix and match approach with interferometric lithography was employed. Super-resolution capability of interferometric lithography was applied to pattern nanoscale Si wires, while optical lithography was used to pattern non-critical device levels. Drain current versus gate voltage measurements of planar and wire MOSFETs demonstrated the superiority of the multiple nanowire gate design. Increasing the number of 0.05 /spl mu/m diameter wires significantly increased current flow in the channel region without sacrificing the low-voltage operation. The mix and match approach for patterning critical level nanoscale features represents a low-cost complement to optical lithography.

Previous research on flyback power factor correction (PFC) converters exposes some inherent shortcomings, such as high‐voltage spike on the metal oxide semiconductor field effect transistor (MOSFET), frequency variation, pulsating input current and hard switching operation. This study presents a new topology for PFC applications named zero‐voltage switching (ZVS) current‐fed flyback converter to not only achieve spike‐free voltage, ZVS on the MOSFETs, but also improve the input current quality. By utilising quasi‐z‐source configuration, the voltage spikes on the MOSFET are effectively eliminated using only a capacitive clamper, resulting in no‐loss consumption. Low‐voltage MOSFETs with low on‐resistance Rds(on) are used to improve the efficiency. In addition, by taking advantage of the average current mode control with the continuous conduction mode operation, the input current perfectly tracks the input voltage. To demonstrate the circuit's feasibility, a 100–140 V input, 28 V/5 A output laboratory prototype was built. The experimental results showed that the proposed topology completely eliminated the voltage spikes on the MOSFETs. The efficiency was improved using low Rds(on) MOSFETs, and ZVS was achieved. In summary, the proposed topology meets the high efficiency and high‐input current quality requirements.

We show that the threshold voltages of both n- and p-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) can be lowered to close to zero by adding extra Schottky contacts on top of nanowires (NWs). Novel complementary metal-oxide-semiconductor (CMOS) inverters are constructed on these Schottky barrier modified n- and p-channel NW MOSFETs. Based on the high performances of the modified n- and p-channel MOSFETs, especially the low threshold voltages, the as-fabricated CMOS inverters have low operating voltage, high voltage gain, and ultra-low static power dissipation.

In this manuscript the authors discuss the issues of designing and implementing an H-Bridge circuit with respect to small switching losses, minimal hardware afford and maximal flexibility of excitation and control. The H-Bridge is targeted for a biomedical Wireless Power Transfer (WPT) application, where the receiver (RX) is small compared to the transmitter (TX) and, thus, negligible. Resonance is applied on the TX side, while the input voltage to the H-Bridge is able to vary in the range of 3V to 28V depending on a flexible relation between the TX and RX. This causes effects to the design and the gate drivers of the H-Bridge. An H-Bridge design is proposed, which includes the use of an n-channel and p-channel Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) for a direct addressing of gates with a microcontroller (μC). In addition, the switching losses are lowered by the introduction of choke inductors and non-overlapping time delayed driving signals. Furthermore, the proposed solution has been verified, since significant advancements compared to state-of-the-art H-Bridge designs can be shown.

The precision of radiation therapy treatment depends on several calibration and quality assurance processes. In-vivo dosimetry (IVD) is used in external beam radiotherapy to evaluate the delivered versus planned dose as a patient-specific quality assurance verification procedure. This study aimed at assessing the performance of diodes (EDP-103G and EDP-203G) and metal oxide semiconductor field-effect transistors (MOSFETs) and corresponding correction factors followed by IVD evaluation in different treatment configurations. Linearity, stability, gantry angle, field size, and source-to-subject distance (SSD) were assessed across various photon energies, with correction factors determined. To minimize patient movement uncertainty, the study utilized the Alderson Rando phantom to replicate clinical setups, comparing diode and MOSFET dose readings to treatment planning system (TPS) doses. Diodes and MOSFETs were evaluated across different photon energy levels for brain, chest, and pelvis planning sites. Diodes and MOSFETs demonstrated good stability and linearity at the different utilized photon beams. Data analysis showed that MOSFETs had a slightly higher sensitivity compared to diodes in gantry angle, field size and SSD corrections. Regarding the validation process after applying the correction factors, dose variations between diode readings and TPS doses were found to be 1.89%, 1.58%, and 6.72% for brain, breast, and pelvis, respectively. In contrast, MOSFET readings were 2.40% for brain, 2.03% for chest, and 2.03% for pelvis. It is concluded that, while diode and MOSFET dosimeters both allowed for accurate patient dose measurements, for different anatomical sites, MOSFETs demonstrated better performance for the pelvis compared to diodes.

The purpose of this work was to estimate skin dose for the patients treated with Tomotherapy using metal oxide semiconductor field-effect transistors (MOSFETs) and thermoluminescent dosimeters (TLDs). In vivo measurements were performed for two head and neck patients treated with tomotherapy and compared to TLD measurements. The measurements were subsequently carried out for five days to estimate the inter-fraction deviations in MOSFET measurements. The variation between skin dose measured with MOSFET and TLD for first patient was 2.2%. Similarly, the variation of 2.3% was observed between skin dose measured with MOSFET and TLD for second patient. The Tomotherapy treatment planning system overestimated the skin dose as much as by 10-12% when compared to both MOSFET and TLD. However, the MOSFET measured patient skin doses also had good reproducibility, with inter-fraction deviations ranging from 1% to 1.4%. MOSFETs may be used as a viable dosimeter for measuring skin dose in areas where the treatment planning system may not be accurate.

Changes in the direct gate tunneling current are measured for strained p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) on (100) wafers for uniaxial and biaxial stress. Decreases/increases in the gate tunneling current for various stresses primarily result from repopulation into a subband with a larger/smaller out-of-plane effective mass. Strain-induced changes in the valence band offset between Si and SiO2 are also important but play a secondary role. Hole tunneling current is found to decrease for biaxial and uniaxial compressive stress and increase for biaxial tensile stress. The hole tunneling data is modeled using k∙p self-consistent solution to Poisson and Schrödinger’s equation, and a transfer matrix method.

A way to improve the metal–oxide–semiconductor field effect transistor (MOSFET) analogue electrical performance, still little explored, is to modify their aspect form or ratio (AR) by the use of innovative layout styles. The diamond MOSFET (DM) is an example of this approach. It presents hexagonal gate geometry. This new layout structure for MOSFET induces two additional effects in comparison with the conventional (i.e. rectangular gate geometry) MOSFET (CM) counterpart, which improves the device's electrical performance: the longitudinal corner effect (LCE) and parallel association of MOSFET with different channel length effect (PAMDLE). How the diamond layout style (DLS) can significantly enhance the device's frequency response (FR) by using two different integrated circuits’ (IC) complementary metal–oxide–semiconductor (CMOS) manufacturing process technologies (bulk and silicon‐on‐insulator (SOI)) is demonstrated.

The Moore’s law of scaling of metal oxide semiconductor field effect transistor (MOSFET) had been a driving force toward the unprecedented advancement in development of integrated circuit over the last five decades. As the technology scales down to 7 nm node and below following the Moore’s law, conventional MOSFETs are becoming more vulnerable to extremely high off-state leakage current exhibiting a tremendous amount of standby power dissipation. Moreover, the fundamental physical limit of MOSFET of 60 mV/decade subthreshold slope exacerbates the situation further requiring current transport mechanism other than drift and diffusion for the operation of transistors. One way to limit such unrestrained amount of power dissipation is to explore novel materials with superior thermal and electrical properties compared to traditional bulk materials. On the other hand, energy efficient steep subthreshold slope devices are the other possible alternatives to conventional MOSFET based on emerging novel materials. This dissertation addresses the potential of both advanced materials and devices for development of next generation energy efficient integrated circuits. Among the different steep subthreshold slope devices, tunnel field effect transistor (TFET) has been considered as a promising candidate after MOSFET. A superior gate control on source-channel band-to-band tunneling providing subthreshold slopes well below than 60 mV/decade. With the emergence of atomically thin two-dimensional (2D) materials, interest in the design of TFET based on such novel 2D materials has also grown significantly. Graphene being the first and the most studied among 2D materials with exotic electronic and thermal properties. This dissertation primarily considers current transport modeling of graphene based tunnel devices from transport phenomena to energy efficient integrated circuit design. Three current transport models: semi-classical, semi-quantum and numerical simulations are described for the modeling of graphene nanoribbon tunnel field effect transistor (GNR TFET) where the semi-classical model is in close agreement with the quantum transport simulation. Moreover, the models produced are also extended for integrated circuit design using Verilog-A hardware description language for logic design. In order to overcome the challenges associated with the band gap engineering for making graphene transistor for logic operation, the promise of graphene based interlayer tunneling transistors are discussed along with their existing fundamental physical limitation of subthreshold slope. It has been found that such interlayer tunnel transistor has very poor electrostatic gate control on drain current. It gives subthreshold slope greater than the thermionic limit of 60 mV/decade at room temperature. In order to resolve such limitation of

The Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) fabricated on a Silicon-On-Insulator (SOI) substrate is effective to suppress Short Channel Effect (SCE), and is one of the most promising electron devices for Very Large Scale Integration (VLSI) circuits for higher speed, higher integration density, and lower power consumption, and it has been already demonstrated that SCE in deep submicron SOI MOSFETs comes from Drain-Induced Barrier Lowering (DIBL) at SOI/Buried OXide (BOX) interface by the author's group. This paper elucidates the roles of permittivity and thickness of BOX layers in suppressing the DIBL in SOI MOSFETs by performing numerical device simulations of SOI MOSFETs with various permittivity and thickness of BOX systematically and by visualizing distribution of dielectric flux lines and current flow lines as well as contour potential lines in MOSFETs.