Using Binary Decision Diagram for Test Generation of Power Supply Noise in Digital Circuits

With the complexity of integrated circuits is continually increasing, a local defect in circuits may cause multiple faults. The behavior of a digital circuit with a multiple fault may significantly differ from that of a single fault. A new method for the detection of multiple faults in digital circuits is presented in this paper, the method is based on binary decision diagram (BDD). First of all, the BDDs for the normal circuit and faulty circuit are built respectively. Secondly, a test BDD is obtained by the XOR operation of the BDDs corresponds to normal circuit and faulty circuit. In the test BDD, each input assignment that leads to the leaf node labeled 1 is a test vector of multiple faults. Therefore, the test set of multiple faults is generated by searching for the type of input assignments in the test BDD. Experimental results on some digital circuits show the feasibility of the approach presented in this paper.

The binary decision diagram is a graph representation of Boolean functions, it also can efficiently represent the logic functionality of digital circuits. The number of nodes in binary decision diagram depends on the variable ordering. A new method is presented in this paper for the variable ordering and the minimization of binary decision diagram, the method is based on adaptive hierarchy genetic algorithm, which uses two populations with hierarchy to evolve in parallel, and the operation parameters in the evolution procedure are adjusted dynamically as the changes of environment. The individual representation scheme corresponding to binary decision diagram, and the implementation steps of adaptive hierarchy genetic algorithm, are given in detail. Besides, the application of the method for the test generation of digital circuits is given. A lot of experimental results show that the binary decision diagrams with smaller number of nodes can be obtained by the method proposed in this paper, and the test vectors of faults in digital circuits can also be produced.

Power supply noise (PSN) has become a critical issue during high-quality at-speed testing. Discrepancies between the circuit's switching activity during functional and test mode can cause overtesting and lead to yield loss. Alternatively, reduced PSN effects around critical paths can result in undertesting the chip, causing test escapes. To achieve a high-quality at-speed test, it is necessary to solve these problems simultaneously. Our previous work introduced a noise index model (NIM), which can be used to predict the mismatch between expected and real path delays. This paper quantitatively investigates and compares NIM values for critical paths during functional and test mode. We then propose a test pattern modification method that harnesses the NIM. The method fills a subset of the don't care bits in partially specified test vectors such that the worst observed functional NIM for the targeted critical path is replicated during test mode.

SUMMARY This paper demonstrates a power supply noise reductionusing on-board stubs. A quarter-length stub attached to the power supplyline of an LSI chip works as a band-eliminate filter, and suppresses thepower supply noise of the designed frequency. Preliminary experimentsshow that 87% of the designed frequency noise component is suppressedwhen stub patterns are written on a power supply area on a PCB board fora 1.25GHz operating LSI. The results show the possibility of the stub on-chip integration when the operating frequency of LSIs becomes higher andthe stub length becomes shorter. key words: stub, on-board, power supply noise, di / dt noise, PRBS pattern 1. Introduction As the process technology advances, the number of transis-tors on an LSI chip has been increasing and their high speedoperation generates more power supply noise while the lowsupply voltage reduces the noise margin. Thus, the powersupply noise becomes a serious issue for the reliability ofthe LSI operations.Recently, a

ABSTRACTThis article provides information on sources of different types of noise in circuits and their deleterious effects, and provides recommendations to mitigate their impact on circuits and systems. The effects of noise on circuit and system performance are discussed, followed by the characteristics of noise from electrical and non-electrical sources. Good circuit layout considerations are provided, including grounding, shielding, and filtering.

We present a new algorithm for generating tests for single stuck line (SSL) faults in combinational logic circuits using a combination of Boolean and path-oriented techniques. We use Boolean techniques employing the ordered binary decision diagram (BDD) to limit the effect of hard faults on the performance of the algorithm. We use path-oriented techniques similar to those in conventional test generation algorithms to limit the number of algebraic operations that must be performed. The test set generated for each fault is exhaustive in the sense that we find all test patterns which make the fault observable at some primary output. We implemented the algorithm as the program TSUNAMI and applied it to the standard ISCAS '85 and ISCAS '89 benchmark circuits. Results indicate that for circuits which are amenable to analysis by BDD's, TSUNAMI performs significantly better than conventional algorithms such as FAN or EST in generating tests for all targeted faults. Moreover, TSUNAMI finds a large set of test vectors for each fault. The program can easily manipulate these sets of vectors to produce test vectors which test many faults. As a result, we are able to compress the sets of vectors into a very small total number of patterns.

The improvement in Integrated Circuits density increases the fault occurrence probability. To ensure proper operation of critical systems, circuits testing becomes a task of extreme importance. Over the years, several methods have been proposed to optimize ATPGs (Automatic Test Pattern Generation). The optimization in test pattern generation aims to reduce the set of test vectors to be applied to circuits. Several techniques explore the concept of equivalent faults (Fault Collapsing). BDDs (Binary Decision Diagram) are one of the data structures explored to solve the problem. With a low capacity to handle large circuits, many extensions and modifications in BDDs have been proposed in the literature. This work aims to review Fault Collapsing concepts and investigate the efficiency of the BDDs proposed in the literature. A case study is done to compare classic techniques with BDDs extensions.

We have compared the power supply noise tolerance of a synchronous processor and a self-timed processor fabricated using 0.18mum CMOS. We have designed the self-timed processor using the same RTL as the synchronous processor, and translated it into a netlist with DCVSL circuits and completion logic trees. We have demonstrated the synchronous processor shows an error rate of 9.3% for the worst power supply noise in case of 10% timing margin design. On the other hand, the self-timed processor shows 40% speed degradation, but no error, for the same power supply noise.

Power integrity design has been becoming important in the advanced CMOS digital systems, because power supply noise induces logic instability and electromagnetic radiation. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation, and result in large electromagnetic radiation. In this paper, effects of damping condition of the total PDN impedance on power supply noise have been studied by adding variable on-die RC circuit to the intrinsic on-die RC circuit in chip PDN. Two types of test chips were designed with different variable on-die PDN impedances. By varying the values of on-die RC circuit, the simulated waveforms of power supply noises for the two test chips have been changed from oscillatory region to damped regions.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

Modern network-on-chip (NoC) systems face reliability issues due to process and environmental variations. The power supply noise (PSN) in the power delivery network of a NoC plays a key role in determining reliability. PSN leads to voltage droop, which can cause timing errors in the NoC. This paper makes a novel contribution towards formally analyzing PSN in NoC systems. We present a probabilistic model checking approach to analyze key features of PSN at the behavioral level in a \(2\times 2\) mesh NoC with a uniform random traffic load. To tackle state explosion, we apply incremental abstraction techniques, including a novel probabilistic choice abstraction, based on observations of NoC behavior. The Modest Toolset is used for probabilistic modeling and verification. Results are obtained for several flit injection patterns to reveal their impacts on PSN. Our analysis finds an optimal flit pattern generation with zero probability of PSN events and suggests spreading flits rather than releasing them in consecutive cycles in order to minimize PSN.

In recent years, in order to handle various sources of noise (including substrate and power supply noises) and process variation in high-end mixed-signal circuit design, analog circuits are often required to be placed symmetrically to the common axis, and high noise digital circuits need to be placed far away from noise interference to the analog blocks. In this paper, we obtain the mixed-signal SoC floorplan with the two-phase approach. In the first phase, we place the symmetry groups and non-symmetry blocks by sequence pair representation with improved implementation. In the second phase, we obtain a floorplan with minimized digital blocks noise interference to analog blocks by the effective decap fills with substrate noise model. We have compared our experimental results with the recent works in symmetry constraints and mixed-signal SOC floorplan with minimized substrate noise. The results demonstrate the effectiveness of our approach.

This paper presents the design and implementation of a Field Programmable Gate Array (FPGA)-based two-channel digital class-D amplifier with H-bridge power stages. Because in H-bridge power stages the power supply noise can intermodulate with the input signals to cause errors in the outputs, a power supply noise measurement circuit and two correction blocks are employed in the proposed amplifier to correct the errors. An experimental measurement platform with a 55 V linear unregulated power supply was built to measure the proposed amplifier. The results obtained show that the errors caused by the power supply noise can be corrected in the proposed amplifier and the Total Harmonic Distortion + Noise (THD+N) of the proposed amplifier is 0.039% with 1 kHz, -1 dBFS input.

In this article, jitter and phase noise of all-digital phase-locked loop due to power supply noise (PSN) with deterministic frequency are analysed. It leads to the conclusion that jitter and phase noise heavily depend on the noise frequency. Compared with jitter, phase noise is much less affected by the deterministic PSN. Our method is utilised to study a CMOS ADPLL designed and simulated in SMIC 0.13 µm standard CMOS process. A comparison between the results obtained by our method and those obtained by simulation and measurement proves the accuracy of the predicted model. When the digital controlled oscillator was corrupted by PSN with 100 mVpk-pk, the measured jitters were 33.9 ps at the rate of fG = 192 MHz and 148.5 ps at the rate of fG = 40 MHz. However, the measured phase noise was exactly the same except for two impulses appearing at 192 and 40 MHz, respectively.

The on-chip decoupling capacitors are widely used in today's high-performance microprocessor design to mitigate the power supply noise problem. The continued reduction of oxide thickness in advanced nanotechnology, however, also significantly increases the tunneling current and leakage power of thin-oxide capacitors. This paper describes the modeling and simulation of a complete chip and package power supply distribution network, and the optimization of the placement of thin-oxide and thick-oxide capacitors to reduce the tunneling current, leakage power, and burn-in cost, while limiting the power supply noise within noise margin.