Using model driven engineering to reliably accelerate early Low Power Intent Exploration for a system-on-chip design

With the current trend of individuals seeking more advanced and intelligent devices in their daily lives, artificial intelligence (AI) chips have become the primary focus for numerous industries. To create smarter AI chips, more computing power is often required, which can lead to an increase in power consumption. This paper describes a low power design of the Extreme Learning Machine (ELM) using single voltage power gating methodology to reduce power dissipation without affecting ELM's functionality. This is realized by applying power gating and state retention techniques in logic synthesis and physical design of ELM. First, a register transfer level (RTL) ELM was designed in Verilog based on the C code of ELM. Then, its functionality was verified by the testbench using VCS. Subsequently, Design Compiler (DC) tool, which was set-up with the inclusion of libraries containing power gating components, was used to synthesize the RTL into a netlist. The hotspot module was identified by compiling the design along with testbench, and timing constraints. The hotspot is where the power gating was implemented after it was described in Unified Power Format (UPF). Then, power analysis was done in PrimeTime tool. By switching power switch on and off, the total power was decreased from 0.1127V to 0.0784V which is 30.43% reduction. In physical design of ELM, power switches are synthesized in array style. Other physical layout design flow such as floorplan, power network synthesis, placement, and clock tree synthesis (CTS) were also performed.

The integration of domain-specific concepts in a model-driven engineering (MDE) approach raises a number of interesting research questions. There are two possibilities to represent these concepts. The first one focuses on models that contain domain-specific concepts only, i.e. domain-specific modelling languages (DSML). The second one advocates the integration of domain-specific concepts in general-purpose models, using what we will refer to in this paper as domain-specific modelling annotation languages (DSMAL). In this position paper, we argue that each approach is particularly suited for specific activities and specific actors, and show how they can be developed and used together. We also highlight the challenges created by the use of two representations, such as the evaluation of models OCL constraints and the synchronisation between the two representations. As an illustration, we present rbacUML, our approach for integrating role-based access control (RBAC) concepts into an MDE approach.

Much effort in register transfer level (RTL) design has been devoted to developing types of tools. However, given the highly complex nature, and lack of control on RTL design, push-button type synthesis is not accepted by many designers. Interactive design with assistance of algorithms and tools can be more effective if it provides control to the steps of synthesis. In this paper, we propose an interactive RTL design environment which enables designers to control the design steps and to integrate hardware components into a system. Our design environment is targeting a generic RTL processor architecture and supporting pipelining, multicycling, and chaining. Tasks in the RTL design process include clock definition, component allocation, scheduling, binding, and validation. In our interactive environment, the user can control the design process at every stage, observe the effects of design decisions, and manually override synthesis decisions at will. We present a set of experimental results that demonstrate the benefits of our approach. Our combination of automated tools and interactive control by the designer results in quickly generated RTL designs with better performance than fully-automatic results, comparable to fully manually optimized designs.

Hardware-in-the-loop (HIL) testing is an integral part of the development of power system automation solutions. HIL test beds facilitate system-level testing and validation of controllers against their specifications. The information required for HIL test bed configurations is typically scattered across different tools used in the development of power system automation solutions. These tools often have different formats and naming schemes. This implies that a significant effort is required for consolidating data from the tools and for creating valid test configurations from the consolidated data. This paper presents a Model-Driven Engineering (MDE) approach for creating HIL test configurations in a tool-, platform-, and protocol-agnostic manner. It shows how the MDE approach can be applied in practice to derive test configurations based on the information originating from different tools in a semi-automated fashion.

Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design flows are available. Unfortunately, equivalent design flows at transactional level are missing. In this paper we describe how a power/clock intent could be described at transactional level using a separation of concerns process and how the transactional simulation code merging functional and power behaviors can be generated automatically using a model-driven engineering approach.

The specific requirements of developing Internet of Things (IoT) software for public transportation systems should be considered in addition to the problems always observed in IoT system development. After defining the problems encountered in the development of IoT-based public transport systems, the current model-driven engineering (MDE) approaches for IoT development are examined and their applicability for public transport systems is questioned in this paper. Several points of view are given about what new MDE approaches specific to this field should include in order to eliminate the identified deficiencies. Moreover, it is indicated that new MDE approaches should be designed including round-trip engineering to provide high mobility, use of special standards, in-vehicle communication networks and support for different system-on-chips in these public transportation systems.

To provide designers with an efficient low power design flow, several methodologies have been proposed such as the Unified Power Format (UPF). The main issue faced by designers is the non-interoperability of those methods across different Computer Aided Design (CAD) tools. Although the UPF standard was originally created with interoperability in mind, few of its constructs are actually supported by all CAD vendors. In this paper, we aim at providing a UPF 2.0 methodology that is compatible with different tools. The proposed case study is a circuit with three power domains and a cross-vendor UPF specification. This paper demonstrates a full low power design flow, with formal power checking, power aware simulation, synthesis and back-end.

During the last decade, Model Driven Engineering (MDE) has been proposed for supporting the development, maintenance and evolution of software systems. Model Driven Architecture (MDA), Software Factories and Eclipse Modeling Framework (EMF) are among the most representatives MDE approaches. Nowadays, it is well recognized that model transformation is at the heart of MDE approaches and, consequently represents one of the most important operations in MDE. However, despite the multitude of model transformation language proposals emerging from academic world and industry, these transformations are often manually specified; which is a tedious and error-prone task, and therefore an expensive process. Matching operation between metamodels is the keystone toward a (semi-)automatic transformation process. In this paper, the authors review metamodel matching techniques of the literature and then analyze their pros and cons in order to show how they can be useful for a semi-automatic transformation process. The result is a comparison of metamodel matching techniques, highlighting their similarities and differences in terms of information used for matching, demonstrating significant similarities between these techniques. Next, the authors compare four well-known metamodel matching techniques namely Similarity flooding, SAMT4MDE+ (extended Semi-Automatic Matching Tool for Model Driven Engineering), ModelCVS and AML (AtlanMod Matching Language) on ten couples of metamodels. For this comparison, the authors define a set of six criteria inspired from the database schema matching. One among these criteria is relevant to the quality of matching and for which we define a quality measure metrics. Furthermore, the authors develop a plug-in under Eclipse to support our comparison using ten couples of metamodels.

Model-Driven Engineering (MDE) is changing the way we build, operate, and maintain our software-intensive systems. Several projects using MDE practices are reporting significant improvements in quality and performance but, to be able to handle these projects, software engineers need a set of technical and interpersonal skills that are currently not widely available. The MDE postgraduate diploma intends to fill this gap by offering a full-time one year formation onMDE. The course syllabus is designed to teach students how to work at a higher abstraction level by the rigorous use of (software) models as the main artifacts in all software engineering activities. Contents include the conceptual framework of MDE plus all techniques and tools (e.g. for defining modeling languages, models, and model transformations) required to successfully complete software engineering projects following a MDE approach. The organizational impact (and challenges) of adopting MDE are exemplified using real industrial experiences. This article describes the MDE Diploma and the lessons that we learned after completing its first edition.

Nowadays, Web Applications (WAs) are complex software sys- tems, used by multiple users with different roles and often devel- oped to support and manage business processes. Due to the chang- ing nature of the supported processes, WAs need to be easily and quickly modified, to adapt and align them to the processes they support. In recent years, Model Driven Engineering (MDE) ap- proaches have been proposed and used to develop and evolveWAs. However, the definition of appropriate MDE approaches for the de- velopment of flexible process-centric WAs is still limited. In par- ticular, (flexible) workflow models have never been integrated with the models (e.g., presentation, information models) used in MDE approaches to develop this type of applications. In this paper, we present M3D (Model Driven Development with Declare), a tool for developingWAs that integrates three MDE metamodels used to represent the main components of aWA with the metamodel of De- clare, a declarative language to model business processes. The tool exploits and combines the declarative nature of Declare and the ad- vantages of MDE to get an efficient roundtrip engineering support to develop and evolve flexible process-centric WAs.

Power reduction is nowadays becoming the first consideration in VLSI design. Low power is one of major concerns in deeply scaled CMOS technologies. There have been many methods in very wide rang to achieve this objective. And the Register-Transfer level (RTL) has become the most effective stage in low power VLSI design, according to the significant power optimization impact and accurate power estimation. In this paper, some respective low power design techniques at RTL are re-investigated at tsmc 45 nanometer CMOS technology. Clock gating (CG) is one of the most widely used and effective technique in RTL low power design. Without the enable signal, bus-specific clock gating (BSC) and threshold-based clock gating (TCG) are considered. Also an improved active-driven optimized bus-specific clock gating (OBSC) is proposed in our laboratory. When the enable signal is taken into account, this paper explains local-explicit clock gating (LECG), enhanced clock gating (ECG), waste-toggle-rate-based (WTR) clock gating and the single comparator-based clock gating (SCCG) techniques. Operand isolation is another useful design technique for reducing the power consumption by blocking some redundant operations. Memory splitting is an effective design solution for low power design as well. These techniques have been experimented by using tsmc 45nm technology library and the proposed low-power RTL techniques are evaluated at gate level with logic synthesis results.

Today's Web Applications (WAs) are complex multi-user and multi-tenant software systems, used by users with different roles and often developed to support and manage complex business processes. Due to the changing nature of such processes, WAs need to be easily and quickly modified, to be adapted and aligned to the processes they support. In recent years, Model Driven Engineering (MDE) approaches have been used to support the development and the evolution of WAs. However, the definition of appropriate MDE approaches for the development of flexible process-centric WAs is still limited. In particular, flexible workflow models have never been integrated with the models used in MDE approaches to develop this type of applications. This paper proposes an MDE approach for the development and the evolution of flexible process-centric WAs that integrates four MDE metamodels used to represent the main components of a WA with the metamodel of Declare, a declarative language to model business processes. A case study, carried out to validate the feasibility, the correctness and the effectiveness of the proposed approach is presented and discussed.

Transaction-level modeling is used in hardware design for describing designs at a higher level compared to the register-transfer level (RTL) (e.g. Cai and Gajski in CODES+ISSS '03: proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 19---24, 2003; Chen et al. in FMCAD '07: proceedings of the formal methods in computer aided design, pp. 53---61, 2007; Mahajan et al. in MEMOCODE '07: proceedings of the 5th IEEE/ACM international conference on formal methods and models for codesign, pp. 123---132, 2007; Swan in DAC '06: proceedings of the 43rd annual conference on design automation, pp. 90---92, 2006). Each transaction represents a unit of work, which is also a useful unit for design verification. In such models, there are many properties of interest which involve interactions between multiple transactions. Examples of this are ordering relationships in sequential processing and hazard checking in pipelined circuits. Writing such properties on the RTL design requires significant expertise in understanding the higher-level computation being done in a given RTL design and possible instrumentation of the RTL to express the property of interest. This is a barrier to the easy use of such properties in RTL designs. In this paper, we consider specification of interaction properties at the transaction-level and the subsequent encoding of the property and the transaction-level model as a finite-state system for model checking. We discuss how the encoded finite-state system can be automatically generated from the specification of the property and the transaction-level model, and illustrate this through simple examples.

According to Moore's Law, number of transistors on chip doubles in every next two years, So the complexity of the circuit increases. So it needs to be careful in designing and verification. Register Transfer Level (RTL) designing and its verification is also most important part of circuit design. The intent behind verification is to check that design meets all system specification and requirements or not. It is important to verify RTL before simulation and synthesis the design because It save clock cycle and time of simulation. This paper is focused on the RTL verification tool, Such as HAL linting and Spyglass RTL signoff tool. This type of RTL verification is used to find bugs and error in design before synthesis. It is easy to debug RTL design and pinpoint the problem and their solution. It is important to identify design issues as early as possible before synthesis RTL design.

Model Driven Engineering (MDE) is a software development approach family based on the use of models in the software construction. It allows the exploitation of models to simulate, estimate, understand, communicate and produce code.Mobile agents are a very interesting technology to develop applications for mobile and distributed environments. A mobile agent is essentially a computer program that acts autonomously on behalf of a user and travels through a network of heterogeneous computers. By moving to remote computers, the mobile agent processes data there and hence saves remote communications and local computation.Many mobile-agent platforms have been developed. While some of them have been abandoned, others continue to release new versions that fix bugs detected or offer new interesting features.In this paper, we present a reflection on how one can realize the migration operation when the mobile-agent applications are built using an MDE approach.