VHMP: A High-efficacy and Parallel Processing Approach for CGRCA Supporting Virtual Heterogeneous Multi-core and Intra-core Multitask Pipeline

Coarse-grain reconfigurable arrays (CGRAs) are emerging accelerators that promise low-power acceleration of compute-intensive loops in applications. The acceleration achieved by CGRA relies on the efficient mapping of the compute-intensive loops by the CGRA compiler, onto the CGRA architecture. The CGRA mapping problem, being NP-complete, is performed in a two-step process, namely, scheduling and mapping. The scheduling algorithm allocates timeslots to the nodes of the data flow graph, and the mapping algorithm maps the scheduled nodes onto the processing elements of the CGRA. On a mapping failure, the initiation interval (II) is increased and a new schedule is obtained for the increased II. Most previous mapping techniques use the iterative modulo scheduling (IMS) algorithm to find a schedule for a given II. Since IMS generates a resource-constrained as-soon-as-possible (ASAP) scheduling, even with increased II, it tends to generate a similar schedule that is not mappable. Therefore, IMS does not explore the schedule space effectively. To address these issues, this article proposes CRIMSON, compute-intensive loop acceleration by randomized IMS and optimized mapping technique that generates random modulo schedules by exploring the schedule space, thereby creating different modulo schedules at a given and increased II. CRIMSON also employs a novel conservative test after scheduling to prune valid schedules that are not mappable. From our study conducted on the top 24 performance-critical loops (run for more than 7% of application time) from MiBench, Rodinia, and Parboil, we found that previous state-of-the-art approaches that use IMS, such as RAMP and GraphMinor could not map five and seven loops, respectively, on a 4×4 CGRA, whereas CRIMSON was able to map them all. For loops mapped by the previous approaches, CRIMSON achieved a comparable II.

Layered video multicast with retransmissions (LVMR) is a system for distributing video using layered coding over the Internet. The two key contributions of the system are: (1) improving the quality of reception within each layer by retransmitting lost packets given an upper bound on recovery time and applying an adaptive playback point scheme to help achieve more successful retransmission, and (2) adapting to network congestion and heterogeneity using hierarchical rate control mechanism. This paper concentrates on the rate control aspects of LVMR. In contrast to the existing sender-based and receiver-based rate control in which the entire information about network congestion is either available at the sender (in sender-based approach) or replicated at the receivers (in receiver-based approach), the hierarchical rate control mechanism distributes the information between the sender, receivers, and some agents in the network in such a way that each entity maintains only the information relevant to itself. In addition to that, the hierarchical approach enables intelligent decisions to be made in terms of conducting concurrent experiments and choosing one of several possible experiments at any instant of time based on minimal state information at the agents in the network. Protocol details are presented in the paper together with experimental and simulation results to back our claims.

Computerisation in healthcare is more general and monitoring intensive care units (ICUs) is more significant and life critical. Accurate monitoring in ICU is essential. Failing to take the right decision at the right time may prove fatal. Similarly, a timely decision can save people's lives in various critical situations. In order to increase the accuracy and timeliness in ICU monitoring, two major technologies can be used, namely parallel processing through vectorisation of ICU data and data communication through internet of things (IoT). With our approach, we can improve efficiency and accuracy in data processing. This paper proposes a parallel decision tree algorithm in ICU data to take faster and accurate decisions on data selection. The uses of parallelised algorithms optimise the process of collecting a large set of patient information. Decision tree algorithm is used for examining and extracting knowledge-based data from large databases. Finalised information will be transferred to concerned medical experts in case of medical emergency using IoT. Parallel implementation of decision tree algorithm is implemented with threads and output data is stored in local IoT table for further processing.

Coarse Grained Reconfigurable Arrays (CGRAs) are a promising class of architectures for accelerating applications using a large number of parallel execution units for high throughput. While they are typically good at utilizing many processing elements for a single task with automatic parallelization, all processing elements are required to perform their operations in lock step; this makes applications that involve multiple data streams, multiple tasks, or unpredictable schedules more difficult to program and use their resources inefficiently. Other architectures like Massively Parallel Processor Arrays (MPPAs) are better suited for these applications and excel at executing unrelated tasks simultaneously, but the amount of resources easily utilized for a single task is limited. We are developing a new architecture with the multi-task flexibility of an MPPA and the automatic parallelization of a CGRA. A key to the flexibility of MPPAs is the ability for subtasks to execute independently instead of in lock step with all other subtasks on the array. In this paper, we develop the special network and control circuitry to add support for this execution style in a CGRA with less than 2% area overhead. Additionally, we also describe the CAD tool modifications and application developer guidelines for utilizing the resulting hybrid CGRA/MPPA architecture.

Coarse-grained reconfigurable arrays (CGRAs) have emerged as promising candidates for digital signal processing, biomedical, and automotive applications, where energy efficiency and flexibility are paramount. Yet existing CGRAs suffer from the Amdahl bottleneck caused by constrained control handling via either off-device communication or expensive tag-matching mechanisms. More importantly, mapping control flow onto CGRAs is extremely arduous and time-consuming due to intricate instruction structures and hardware mechanisms. To counteract these limitations, we propose Raccoon, a portable and lightweight framework for CGRAs targeting vast control flows. Raccoon comprises a comprehensive approach that spans microarchitecture, HW/SW interface, and compiler aspects. Regarding microarchitecture, Raccoon incorporates specialized infrastructure for branch- and loop-level control patterns with concise execution mechanisms. The HW/SW interface of Raccoon includes well-characterized abstractions and instruction sets tailored for easy compilation, featuring custom operators and architectural models for control-oriented units. On the compiler front, Raccoon integrates advanced control handling techniques and employs a portable mapper leveraging reinforcement learning and Monte Carlo tree search. This enables agile mapping and optimization of the entire program, ensuring efficient execution and high-quality results. Through the cohesive co-design, Raccoon can empower various CGRAs with robust control-flow handling capabilities, surpassing conventional tagged mechanisms in terms of hardware efficiency and compiler adaptability. Evaluation results show that Raccoon achieves up to a 5.78× improvement in energy efficiency and a 2.24× reduction in cycle count over state-of-the-art CGRAs. Raccoon stands out for its versatility in managing intricate control flows and showcases remarkable portability across diverse CGRA architectures.

A key aspect of Coarse-Grained Reconfigurable Arrays (CGRAs) is dynamic reconfigurability, where multiple configurations, or contexts, are loaded into the CGRA to time-multiplex its resources. This feature allows the CGRA to accommodate larger applications without a significant increase in its size. Context switching is typically centralized, using the system clock to synchronously cycle through configurations simultaneously across CGRA resources. This approach is unable to efficiently accommodate variable-latency operations. Elastic CGRAs were proposed to handle such operations via an architecture that operates according to a dataflow paradigm. However, elastic solutions are single context by nature, which limits their applicability to smaller application kernels. Time-multiplexed multi-context and elastic CGRAs are thus naturally incompatible with one another. In this paper, we aim to overcome this incompatibility and propose an architectural framework that is capable of generating elastic CGRAs with multi-context support. Elastic primitives that traverse contexts in a distributed fashion are introduced. We also extend conventional mapping solutions to handle the new architectures. Finally, we evaluate the area and performance overhead for elastic multi-context CGRAs over single context ones with equal processing capacity.

This paper proposes an approach to design a quadruped robot with a dynamic spine using Reservoir Computing. Four bending sensors are integrated into the continuous dynamics spine to adjust spine force for balancing and enable closed-loop control of the Center of Mass (CoMs) mapping onto the dynamic surface. Passively modeling the system enabled a quadrupedal robot with a flexible spine to navigate rough terrain with improved efficiency, agility, and minimized impact on explosive power. Additionally, paper introduce to develop a novel, intelligent control mechanism for the quadrupedal robot to operate effectively on dynamic, flexible surfaces. Our approach focuses on a hierarchical distributed control mechanism developed for leg to cooperatively change centralized frames for a better functional reflection.

The heterogeneity and the complexity of the communication network in current use are great difficulties in building the actual information dissemination management (IDM) systems. These difficulties bring big technical challenges to IDM for communications resource management, transmission control, information catalogue/search and transmitting. A generic information dissemination management method based on hierarchical strategy control mechanism is proposed in this research in order to deal with the problem in an economic and efficient way. The hierarchy, the working process and model, the control mechanism and application about strategies of information dissemination management systems are all discussed in the research.

This paper presents a task level mapping flow for coarse-grained dynamic reconfigurable array processor based on static thermal-aware mapping techniques. The flow is composed of front-end SUIF tool, temporal partitioning algorithm, thermal aware sub-graph mapping algorithms and back-end RAM compiler to compile HLL task into binary code for the processor automatically. Using compact thermal model, the temperature distribution of each task sub-graph on reconfigurable RC array is pre-estimated statically. The runtime sequence of all task sub-graphs is generated ultimately with the random searching algorithm to balance the reconfigurable array's temperature. Experimental results show that the average maximum temperature and temperature distribution range can be reduced about 6.3°C and 12°C, respectively.

Coarse-grained reconfigurable arrays (CGRAs), loosely defined as arrays of functional units (e.g., adder, subtractor, multiplier, divider, or larger multi-operation units, but smaller than a general-purpose core) interconnected through a Network-on-Chip, provide higher flexibility than domain-specific ASIC accelerators while offering increased hardware efficiency with respect to fine-grained reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs). The fast evolving fields of machine learning and edge computing, which are seeing a continuous flow of novel algorithms and larger models, make CGRAs ideal architectures to allow domain specialization without losing too much generality. Designing and generating a CGRA, however, still requires to define the type and number of the specific functional units, implement their interconnect and the network topology, and perform the simulation and validation, given a variety of workloads of interest. In this paper, we propose OpenC-GRA *, the first open-source integrated framework that is able to support the full top-to-bottom design flow for specializing and implementing CGRAs: modeling at different abstraction levels (functional level, cycle level, register-transfer level) with compiler support, verification at different granularities (unit testing, integration testing, property-based testing), simulation, generation of synthesizable Verilog, and characterization (area, power, and timing). By using OpenCGRA, it only takes a few hours to build a specialized power- and area-efficient CGRA throughout the entire design flow given a set of applications of interest. OpenCGRA is available online at https://github.com/pnnl/OpenCGRA.

Coarse-grained reconfigurable cryptographic logic arrays (CGRCAs) have become an important platform for hardware implementation of cryptographic algorithms due to their good balance between performance and flexibility. However, existing CGRCA architectures suffer from low hardware resource utilization and low performance of cryptographic algorithms with chained operation modes (e.g., CBC mode of block cipher algorithms). In this paper, an efficient design method for highperformance and high-resource-utilization CGRCA is proposed. The structural characteristics, data dependencies, and parallelism of symmetric cryptographic algorithms are analyzed to determine the core design requirements of the CGRCA. Moreover, multi-task interleaved pipelining (MTIP) and virtual-path parallel processing (VPP) techniques are adapted to improve the parallel processing capability of the CGRCA. On this basis, a chord-based CGRCA architectural model is built to guide the hardware structure design of the CGRCA architecture. Finally, a Bayesian-based design space exploration (DSE) method is proposed to accurately and efficiently determine the core design parameters of CGRCA. The experimental results show that the CGRCA architecture based on the proposed design method can significantly improve performance and hardware resource utilization compared with the traditional CGRCA architectures.

This paper presents an evaluation of a Heterogeneous Multicore Architecture (HMA) by implementing Orthogonal Frequency-Division Multiplexing (OFDM) receiver blocks as designs for the test of functionality. OFDM receiver consists of computationally intensive and general-purpose processing tasks that can provide maximum coverage to test and evaluate a massively-parallel as well as a general-purpose platform like the HMA. The blocks of the receiver are primarily designed by crafting template-based Coarse-Grained Reconfigurable Array (CGRA) devices and then arranging them in a sequence over a Network-on-Chip (NoC) structure along with a few RISC cores for complete OFDM processing. The OFDM blocks such as Fast Fourier Transform (FFT) and Time Synchronization are computationally intensive and require parallel processing. The OFDM receiver also contains tasks such as frequency offset estimation which require the processing of Taylor series and CORDIC algorithms that are serial in nature. Such a combination of serial and parallel algorithms can perform a thorough exploration and evaluation of almost all the design features of an HMA. The OFDM implementation has led to scale CGRAs to different dimensions, instantiate Processing Elements (PEs) as multiple arithmetic resources and to establish almost all possible ways of PE interconnections. It further explores time-multiplexed patterns for data placement in the CGRA memories. Nevertheless, the data can also be exchanged among different nodes over NoC structure simultaneously and independently by using direct memory access devices. In this experimental work, the performance of each CGRA, the collective performance of the whole platform and the NoC traffic are recorded in terms of the number of clock cycles and several high-level performance metrics. Today's HMAs are generally over or under resourced for the applications that they are designed for and thus not an optimal choice for the end user. Apart from the interesting comparisons to the other state-of-the-art, our experimental setup has provided important insight and guidelines that the designers can use to implement near-optimal solutions for their target applications.

In the study of language comprehension in noisy environments, the Cocktail Party Effect, as a classic cognitive phenomenon, has vividly revealed the selective attentional capacity of the human auditory system. The effect describes the remarkable phenomenon of an individual’s ability to focus on a specific conversation even in the midst of a noisy party, and is essentially a mechanism of selective attention of the attentional control system to key cues of language. Early acoustic processing enhances the efficiency of speech parsing through perceptual preferences developed through everyday language interactions (e.g., voice onset time that reinforces bursts). This cognitive mechanism has a dual significance in noisy language comprehension: on the one hand, it reflects the filtering function underlying attentional control over acoustic interference; on the other hand, its efficiency differences directly reflect the plasticity characterizing the individual’s language processing ability. Based on the theoretical framework of psycholinguistics, this study systematically elucidates the mechanism of hierarchical attentional control for language comprehension in noisy environments, using the cocktail party effect as the entry point. Early acoustic processing enhances speech parsing efficiency through experience-driven perceptual weight adjustments (e.g., voice onset time for reinforcement of bursts); mid-phrase lexical competition resists semantic interference through inhibitory control; and late syntactic processing relies on strategic allocation of working memory resources. Behavioral plasticity is characterized by a significant increase in noise comprehension accuracy due to bilinguals’ inhibitory control, and children with specific language impairment (SLI) showed significant between-group differences in sentence repetition ability under classroom noise through 8 weeks of rhyming attention training, a finding that provides an empirical basis for language teaching.

Control of multiple robots has attracted researchers' interests for many years. Problems arise when uncertainty or coordinated motions are involved. This paper investigates several issues related to control of robot systems with multiple arms. We present a systematic control strategy for the coordination of robot motions during homogeneous manipulations. A hybrid force and position control law is used to determine the force and position targets of the object being manipulated. The frictional equilibrium and stability principles are employed in computing the optimal force distribution among the robots. The position targets for the end effector of individual robots are calculated using appropriate transformations which take into account the coordinating constraints. A generalized control algorithm is developed using this strategy and the manipulation can be achieved by specifying a number of external quantities, which describe the nature of the tasks to be performed, as the inputs to the control algorithm. This control strategy is adopted in developing control algorithms for heterogeneous manipulation tasks such as tasks that require robot interchange during the manipulation. In such as task, it is necessary to coordinate the motions between the coordinating robots and a free robot. A hierarchical control mechanism is used in achieving this coordination. The control primitives developed for controlling robots in the homogeneous manipulation can be used in this hierarchical control. The control algorithms have been successfully implemented on a robot system to perform various tasks with good results.

With the continuing evolution of the variety of digital video formats, a high quality conversion between formats is essential. This paper provides an overview of digital video format conversion and introduces a scalable parallel processing architecture that addresses spacial conversions. Video formats vary by sampling rate, line rate, aspect ratio, frame rate, and scan type. In a conversion between formats, these differences must be resolved through spatial resampling, frame rate conversion, and de-interlacing. — The architecture that is introduced tackles the two dimensional conversion that is needed for the sampling rate, line rate, and aspect ratio discrepancies. A resizing filter is at the heart of this processor for the sample and line scaling that is needed. The high sampling frequencies of high definition formats make it difficult to implement the required digital signal processing functions with existing technology. Therefore, a parallel processing approach is taken that permits processing at a more reasonable clock rate.