Virtual metrology modeling based on gaussian bayesian network

We developed a new accelerated quantum chemical molecular dynamics program called Colors which can simulate the chemical-mechanical polishing (CMP) processes. It is more than 5,000 times faster than the regular first-principles molecular dynamics program, since it is based on our original tight-binding theory. We employed a SiO2 particle as a polishing material. Two types of silicon surfaces, clean Si(100) and H-terminated Si(100) 2×1, were modeled to clarify the effect of the Si surface structure on the dynamic behaviors of the CMP processes. We paid attention to the bond population of the silicon atom during the CMP processes. The bond population of the silicon atom was decreased by the CMP process on both surfaces, indicating that the electronic state of the silicon wafer became unstable due to the CMP process. It is an interesting finding that the hydrogen atoms were desorbed from the H-terminated Si(100) 2×1 surface. The results indicate that our new program can simulate both the chemical reactions and mechanical polishing processes. To the best of our knowledge, this is the first simulator of the CMP processes on the atomic and electronic levels.

The chemical mechanical polishing (CMP) process has become a widely accepted global planarisation technology. The abrasive is one of the important influencing factors during the CMP process. In this work, γ-alumina/silica abrasives with a core–shell structure were synthesised. Time-of-flight secondary ion mass spectroscopy was used to characterise the composition of the obtained abrasives. The morphology and structure of the abrasives were measured by using scanning electron microscopy and transmission electron microscopy. The CMP performances of the γ-alumina/silica abrasives on sapphire substrates were investigated. Experimental results indicate that the γ-alumina/silica abrasives exhibit lower surface roughness and higher material removal rate than that of pure silica and γ-alumina abrasives under the same testing conditions. Furthermore, through the X-ray photoelectron spectroscopy test, this work investigated the chemical effect mechanism of the γ-alumina/silica core–shell abrasives in sapphire CMP. The results show that solid-state chemical reactions occur between the silica shell and sapphire surface during the CMP process. The study also established a wear model to investigate the mechanical friction mechanism.

Rapid estimation of the removal rate of the chemical mechanical polishing (CMP) process of a gallium nitride (GaN) substrate contributes to the quick diagnosis of CMP progressing, leading to accelerated process development. The present study discusses the feasibility of using cathodoluminescence (CL) imaging for a rapid diagnosis of the removal rate of the CMP process. Mechanically induced subsurface damage was detected as black lines in the CL images due to nonradiative recombination. To quantitatively understand the CL images from the GaN substrate, the CL images was analyzed for the mean image brightness. We developed an advanced theory interpreting CL image brightness as a logistical function with the CMP processing time by assuming that the mechanically induced damages at and near the surface exponentially decrease with depth from the surface. Therefore, the CMP progress was successfully characterized by analyzing CL images in CMP process with the logistic functions, which provided a rapid estimation of the CMP removal rate.

A production worthy, Tungsten Chemical Mechanical Polish (CMP) process using a commercially available K103 slurry was developed, characterized, and tested for sub-0.35μm multilevel interconnect fabrication. The effects of pre-tungsten CMP process on tungsten polish are reported in detail. A head-to-head comparison of the optimized KIO3 process with the standard Fe(NO3)3 process is described. Critical CMP tool parameters (process and hardware) were flexed using statistically valid experimental designs. The advantages and disadvantages of a post tungsten polish, oxide buff, are discussed. Across-wafer non-uniformity, specifically the enhanced polish rate of tungsten at the wafer edge, was significantly reduced with the optimized process parameters and hardware setup. Also, an automated endpoint system was utilized and a set of robust endpoint algorithms were developed to minimize the amount of oxide loss during tungsten CMP processing. Finally, the positive effects of the optimized KIO3 tungsten CMP process on interconnect integration and die yield are reported.

A signal processing method for the friction-based endpoint detection system of a chemical mechanical polishing (CMP) process is presented. The signal process method uses the wavelet threshold denoising method to reduce the noise contained in the measured original signal, extracts the Kalman filter innovation from the denoised signal as the feature signal, and judges the CMP endpoint based on the feature of the Kalman filter innovation sequence during the CMP process. Applying the signal processing method, the endpoint detection experiments of the Cu CMP process were carried out. The results show that the signal processing method can judge the endpoint of the Cu CMP process.

This paper present a high-quality polysilicon oxide combining N/sub 2/O nitridation and chemical mechanical polishing (CMP) processes. Experimental results indicate that polyoxide grown on the CMP sample exhibits a lower leakage current, higher dielectric breakdown field, higher electron barrier height, less electron trapping rate, higher charge-to-breakdown (Q/sub bd/), and lower density of trapping charge than those of non-CMP samples. In addition, the CMP process enhances nitrogen incorporation at the interface by the N/sub 2/O nitridation, ultimately improving the polyoxide quality. However, the CMP process smooths the surface of polysilicon and this planar surface reduces the out-diffusion of the phosphorous during thermal oxidation.

Chemical mechanical polishing (CMP) is an essential semiconductor manufacturing process because of its local and global planarization ability in fabricating highly integrated devices. The CMP process uses both chemical reaction and mechanical polishing simultaneously. The combination of chemical reaction and mechanical removal in CMP is so complex that understanding the material removal mechanism has been a challenge for researchers and engineers. The chemical reaction mechanism is determined by the chemical composition of the CMP slurry and the material property of the target material. However, the mechanical action is a complex result of various mechanical factors of the process parameters and consumables. The mechanical material removal is a cornerstone of understanding and predicting CMP results. This review focuses on the mechanical aspects in CMP in terms of the process parameters and consumables of the CMP process that directly influence the material removal characteristics.

The fabrication of through-silicon vias (TSVs) is a major component in the development of three-dimensional (3D) integration technology and advanced 3D packaging approaches. The large diameter and length of TSVs, as compared to traditional interconnects, create some unique process challenges. Via plating and chemical-mechanical polishing (CMP) processes used in standard copper interconnect technology are generally not suitable for TSV fabrication. Therefore, efforts are being made to develop such processes specifically for TSV technology. This paper will describe the development of a void-free Cu electroplating process for TSV filling, along with CMP processing to remove the overburden layer and expose the Cu-filled vias for subsequent metallization. The focus of the paper will be the integration of the TSV plating and CMP processes, with discussion regarding observed integration challenges and their solutions. First, a Cu electroplating process was developed for defect-free, bottom-up filling of silicon vias from 20-200 μm in diameter and 150-375 μm deep, with aspect ratios from 1:1 to 8:1. Next, CMP tests were conducted using Cu-filled silicon vias of 50 μm diameter and 150 μm depth, designed for use in a MEMS wafer-level packaging application. These tests indicated that plating nonuniformity and Cu mound defects over filled vias caused significant CMP process issues. The plating process was then modified to eliminate these problems in the Cu films, resulting in improved CMP uniformity and reduced polishing time.

As we move to more advanced nodes, the number of Chemical Mechanical Polishing (CMP) steps in semiconductor processing is increasing rapidly. CMP is known to suffer from pattern dependent variation such as dishing, erosion, recess, etc., all of which can cause performance and yield issues. One such yield issue seen in back end of line (BEOL) Cu interconnect CMP processes is pooling. Pooling exists when there is uncleared bulk Cu and/or barrier residue remaining after final CMP step, leading to shorts between neighboring interconnect lines. To detect potential pooling locations on a given design, for a given CMP process, predictive CMP models are needed. Such models can also aid in CMP process and chip design optimizations. In this paper we discuss how a pattern dependent CMP effect that we call the “local neighborhood effect” causes large recesses that can lead to pooling in Cu interconnect CMP processes. We also discuss modeling this effect as part of an advanced predictive CMP modeling system and show how the resulting modeling system accurately predicts Cu pooling on several 14 nm designs.

Tungsten chemical mechanical polishing (CMP) has been used for metal interconnect formation in semiconductor manufacturing for a long time. Its application continues to the advanced device manufacturing with transistor scaling. However, the defect concerns of the tungsten CMP process have become critical to manufacturing such as metal flake defects that can cause electrical shorts between contacts. Although there are many published studies on tungsten CMP fundamentals, process applications and CMP-induced defects, the mechanism of thin metal flake formation in nanoscale (nano-flake defect) has not been clearly known to industry. In this study, nano-flake defects are identified after tungsten contact CMP, and mechanism of its formation is explored. Significant CMP dishing at wide contact area removes all tungsten and open barrier metal. Friction force by 3-body interaction among wafer, abrasive particle and pad asperity breaks the adhesion of barrier material from intermetallic dielectric material. And it allows re-deposition of barrier metal to the wafer surface. Insufficient CMP in-situ cleaning results in residual nano-flake defects at the end of CMP process. Analysis of device macros, thickness of flake, cross sectional analysis by transmission electron microscope (TEM) and topographical analysis support this suggested mechanism.

CMP characteristics and optical property of ITO thin film by using silica slurry with a variety of process parameters

The interlayer dielectric (ILD) chemical mechanical polishing (CMP) process was characterized using frictional forces, material removal rates, thermal measurements, and theory. Experiments were performed on a novel 200 mm tribometer in which friction force was acquired in two directions, giving a complete resolution of the force vector in the CMP process. A thermal study of the pad surface was conducted using an infrared video camera to simultaneously measure temperature changes. A Langmuir-Hinshelwood model with a reaction temperature based on a flash heating hypothesis was applied to the experimental data to evaluate the chemical and mechanical contributions during ILD CMP. The results obtained from the 200 mm tribometer were compared to those from a 100 mm tribometer. Results showed that the scale-up of the ILD process from 100 to 200 mm caused a transition from a mechanically limited regime, in which it was still possible to detect thermal effects, to a higher degree of mechanical limitation where it was no longer possible to detect thermal effects.

Nanosecond laser irradiation assisted chemical mechanical polishing (CMP) process for promoting material removal of single crystal 4H–SiC

ABSTRACTNanotopography refers to 10-100 nm surface height variations that exist on a lateral millimeter length scale on unpatterned silicon wafers. Chemical mechanical polishing (CMP) of deposited or grown films (e.g., oxide or nitride) on such wafers can generate undesirable film thinning which can be of substantial concern in shallow trench isolation (STI) manufacturability. Proper simulation of the effect of nanotopography on post-CMP film thickness is needed to help in the measurement, analysis, diagnosis, and correction of potential problems.Our previous work has focused on modeling approaches that seek to capture the thinning and post-CMP film thickness variation that results from nanotopography, using different modeling approaches. The importance of relative length scale of the CMP process used (planarization length) to the length scale of the nanotopography on the wafer (nanotopography length) has been suggested.In this work, we report on extensive experiments using sets of 200 mm epi wafers with a variety of nanotopography signatures (i.e., different nanotopography lengths), and CMP processes of various planarization lengths. Experimental results indicate a clear relationship between the relative scales of planarization length and nanotopography length: when the planarization length is less than the nanotopography length, little thinning occurs; when the CMP process has a larger planarization length, surface height variations are transferred into thin film thickness variations. In addition to presenting these experimental results, modeling of the nanotopography effect on dielectric CMP processes is reviewed, and measurement data from the experiments are compared to model predictions. Results show a good correlation between the model prediction and the experimental data.

Chemical Mechanical Polishing (CMP) is the essential process for planarization of wafer surface in semiconductor manufacturing. CMP process helps to produce smaller ICs with more electronic circuits improving chip speed and performance. CMP also helps to increase throughput and yield, which results in reduction of IC manufacturer’s total production costs. CMP simulation model will help to early predict CMP manufacturing hotspots and minimize the CMP and CMP induced Lithography and Etch defects ^[2]. In the advanced process nodes, conventional dummy fill insertion for uniform density is not able to address all the CMP short-range, long-range, multi-layer stacking and other effects like pad conditioning, slurry selectivity, etc. In this paper, we present the flow for 20nm CMP modeling using Mentor Graphics CMP modeling tools to build a multilayer Cu-CMP model and study hotspots. We present the inputs required for good CMP model calibration, challenges faced with metrology collections and techniques to optimize the wafer cost. We showcase the CMP model validation results and the model applications to predict multilayer topography accumulation affects for hotspot detection. We provide the flow for early detection of CMP hotspots with Calibre CMPAnalyzer to improve Design-for-Manufacturability (DFM) robustness.