Virtual parallelism allows relaxing the synchronization constraints of SIMD computing paradigm

Two-level pipelining in processor arrays (PAs) involves pipelining of operations across processing elements (PEs) and pipelining of operations in functional units in each PE. Although it is an attractive method for improving the throughput of PAs, existing methods for generating PAs with two-level pipelining are restricted and cannot systematically explore the entire space of feasible designs. In this paper, we extend a systematic design method, called General Parameter Method (GPM), we have developed earlier to find optimal designs of PAs with two-level pipelines. The basic idea is to add new constraints on periods of data flows to include the effect of internal functional pipelines in the PEs. As an illustration, we present pipelined PA designs for computing matrix products. For n-dimensional meshes and other symmetric problems, we provide an efficient scheme to obtain a pipelined PA from a non-pipelined PA using a reindexing transformation. This scheme is used in GPM as a pruning condition to arrive at optimal pipelined PAs efficiently. For pipelines with minimum initiation interval (MII) greater than unity, we show additional constraints that ensure correctness of the synthesized PAs.

We propose a new restructuring method for mesh-connected processor arrays (PAs) using single track shift with spare processing elements (PEs) on the orthogonal two or four sides. First, a method called “ROT method” for mesh-connected PAs with spare PEs on the orthogonal sides is described. Next, the method is applied to mesh-conected PAs with spare PEs on the four sides. The effect of the method is evaluated by computer simulation and it is shown that ROT method makes array reliabilites fairly higher than those of the existing methods for mesh-connected PAs with the same number of spare PEs and the same network structure. The hardware realization of ROT method is also discussed and it is seen that the method can be realized as a simple built-in circuit. The circuit can be embedded in a target PA to reconstruct the PA with faulty PEs very quickly. This implies that the proposed method is especially effective in enhancing the run-time reliability of a PA in mission critical systems where first self-reconfiguration is required without an external host computer or manual maintenance operations.KeywordsFault-toleranceMesh arraySingle track shiftSelf-restructuringBuilt-in circuit

Despite the continuous research to facilitate WSNs development, most safety analysis and mitigation efforts in concurrency are still left to developers, who must manage synchronization and shared memory explicitly. In this paper, we present a system language that ensures safe concurrency by handling threats at compile time, rather than at runtime. Based on the synchronous programming model, our design allows for a simple reasoning about concurrency that enables compile-time analysis resulting in deterministic and memory-safe programs. As a trade-off, our design imposes limitations on the language expressiveness, such as doing computationally-intensive operations and meeting hard real-time responsiveness. To show that the achieved expressiveness and responsiveness is sufficient for a wide range of WSN applications, we implement widespread network protocols and the CC2420 radio driver. The implementations show a reduction in source code size, with a penalty of memory increase below 10% in comparison to nesC. Overall, we ensure safety properties for programs relying on high-level control abstractions that also lead to concise and readable code.

In order to exploit the emerging multi-core processors, creating multi-threaded applications is going to be a necessity. However, resolving concurrency, synchronization, and coordination issues, and tackling the non-determinism germane in multi-threaded software is extremely difficult. Ensuring deterministic behavior and correctness with respect to the specification is necessary for safe execution of such code. It is desirable to synthesize multi-threaded code from formal specifications using a provably 'correct-by- construction' approach. In the past, reasonable success has been achieved in the 'correct-by-construction' sequential software synthesis for embedded reactive systems from synchronous programming models. Here we target deterministic multi-threaded software synthesis from deterministic specifications, such that the behavior of the code is semantically equivalent to that of the specification. We choose the polychronous model of computation for specification because (i) such specifications are multi-rate, reactive, concurrent and can be made deterministic through constraints on the environment, and (ii) formal verification methodologies and tools exist for such specifications. In this paper, we analyze under what condition a polychronous specification can be synthesized into multi-threaded C-code preserving its semantics. We also discuss how the synchronous data flow graph structure for a polychronous specification can be used to infer the threading structure of the resulting C-code.

A systematic efficient fault diagnosis method for reconfigurable VLSI/WSI array architectures is presented. The basic idea is to utilize the output data path independence among a subset of processing elements (PEs) based on the topology of the array under test. The "divide and conquer" technique is applied to reduce the complexity of test application and enhance the controllability and observability of a processor array. The array under test is divided into nonoverlapping diagnosis blocks. Those PEs in the same diagnosis block can be diagnosed concurrently. The problem of finding diagnosis blocks is shown equivalent to a generalizedEight Queens problem. Three types of PEs and one type of switches, which are designed to be easily testable and reconfigurable, are used to show how to apply this approach. The main contribution of this paper is an efficient switch and link testing procedure, and a novel PE fault diagnosis approach which can speed up the testing by at leastO(?V?1/2) for the processor arrays considered in this paper, where ?V? is the number of PEs. The significance of our approach is the ability to detect as well as to locate multiple PE, switch, and link faults with little or no hardware overhead.

In the process of mapping compute-intensive algorithms onto arrays of processing elements (PEs) an efficient usage of channels between PEs and registers within PEs is crucial for achieving a significant algorithm acceleration. In this paper this problem is solved for algorithms represented as systems of uniform recurrence equations. We address an optimization problem in order to realize the algorithmic data dependencies within the processor array (PA) with minimum cost for channels and registers. There, we use a new mapping approach which allows a direct mapping of the algorithm onto the PA by a partitioning method. In contrast to existing approaches, we consider the issue of avoiding redundant usage of channels and registers, which can appear if one instance of a variable has to be transferred from a source PE to several sink PEs. Further, a solution of the optimization problem determines the schedule for the transfer of the variable instances in the channels and their storage in registers as well as the inner schedule for the operations in the PEs. We illustrate our method on the edge detection algorithm.

In the process of mapping compute-intensive algorithms onto arrays of processing elements (PEs) an efficient usage of channels between PEs and registers within PEs is crucial for achieving a significant algorithm acceleration. In this paper this problem is solved for algorithms represented as systems of uniform recurrence equations. We address an optimization problem in order to realize the algorithmic data dependencies within the processor array (PA) with minimum cost for channels and registers. There, we use a new mapping approach which allows a direct mapping of the algorithm onto the PA by a partitioning method. In contrast to existing approaches, the authors consider the issue of avoiding redundant usage of channels and registers, which can appear if one instance of a variable has to be transferred from a source PE to several sink PEs. Further, a solution of the optimization problem determines the schedule for the transfer of the variable instances in the channels and their storage in registers as well as the inner schedule for the operations in the PEs. We illustrate our method on the edge detection algorithm

This paper examines the computing power of optical parallel computer systems. We consider the proposed Array of Processors with optical Pipelined Buses (APPB) in particular, where processors communicate with each other via a spanning optical bus. APPB allow simultaneous access by multiple processors to the optical bus through message pipelining, thus overcoming the bottlenecks caused by exclusive access when employing electronic buses. We give an overview of this model of parallel computation, and then examine the computing power of APPB by demonstrating its capability to efficiently emulate the CRCW PRAM model. We show that an APPB is almost as powerful as a CRCW PRAM. That is, an APPB can emulate a CRCW PRAM with only a small degradation in time performance.

Different standards for video compression require a flexible approach for integrating this functionality into multimedia terminals and computers. A programmable processor array (reduced instruction set computer, dataflow, four processor elements) and the corresponding decoding software are presented for this task. Specifically, the simulation results show that the use of fast algorithms combined with careful programming with respect to the statistical behavior of the coded video data leads to high decoding performance. Therefore, despite the fact that it is universally programmable, the processor array has about the same decoding performance/number of devices ratio as dedicated or hybrid architectures. This means that regular, scalable, and universally programmable processor arrays are competitive solutions for MPEG (Motion Picture Experts Group) video decompression and similar kinds of complex data processing algorithms. >

The architectural design and VLSI implementation of a highly reconfigurable dataflow RISC (DF-RISC) processing element (PE) are presented. This processor forms an element of a processor array (DF-RISC-PA) which possesses the features of both static and dynamic dataflow models. The array can be programmed to execute arbitrary algorithms (recursive or irregular) in both static and dynamic manner. The processor array is modelled at the behavioural level in VHDL. The gate level implementation and VLSI layout of both the PE and the array are obtained with the help of OASIS Silicon compiler by translating the VHDL model to Logic3. Sample computations are mapped to illustrate functionality. The design is validated at all levels of abstraction. The results of simulation of the PE array are presented. The architecture is compared with previous approaches. The prototype PE requires 4261 CMOS gates and uses an area of 7512 × 8081 μm2.

This paper presents a new and improved word-based processor array architecture for unified and scalable radix2 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architecture extracted by Ç. Koç̧, and also the multiplier bits are fed serially to the first processing element of the processor array every odd clock cycle. Moreover, this architecture was modified to reduce the critical path delay and area by replacing the two levels of carry save adder (CSA) logic by modified 4-to-2 CSA that use only one level of dual field adder logic (DFA) taking advantage of processing two operand words by the same processing element (PE) of the processor array. An ASIC Implementation of the proposed architecture shows that it can perform 1024-bit modular multiplication (for word size w = 32) in about 17.07 μs. Also, the results show that it has smaller Area ×Time values compared to all existing designs by ratios ranging from 11.6 % to 47.8 % which makes it suitable for implementations where both area and performance are of concern. Moreover, it has higher throughput (1.8-39.5 %) than most of the published unified and scalable architectures except the architecture extracted by Harris. It has slightly higher throughput (4.5 %) than the proposed one.

Upcoming processor architectures support parallel processing on different levels. Multiple processing elements (PEs) run in parallel. The PEs consists of several functional units and the functional units allow sub-word parallelism (SWP), i.e. the parallel execution of operations with low data word width. In this paper, a parameterized mapping of algorithms onto massively parallel processor architectures (PAs) is derived which exploits both parallelism on PA and SWP on PE level. It establishes a correlation between the parameters of the algorithms and the parameters of the PA, which enables optimization strategies with respect to several expense factors of the PA. The design approach is based on the co-partitioning method and the partitioning of data dependencies. Both are used in a hierarchical manner. Besides the parameters of the PA (such as shape, number of PEs, number of sub-words processed in parallel, channels between the PEs, and their delay), the packing instructions for exploiting SWP can be deduced

The problem of tree pattern matching for object recognition in images is computationally intensive in nature. In two-dimensional images, the objects can be represented through multiscale decomposition as tree structures. The pattern tree representing an object can be matched with a subject tree representing an image in order to detect the objects within the image. In this paper, we describe a new systolic algorithm and its realization as a VLSI chip for tree pattern matching. The hardware algorithm is based on a linear array of processing elements (PEs) where the pattern matching is done in a pipelined fashion relying on nearest-neighbor communication between the PEs and the subject and pattern trees of arbitrary length can be processed using a fixed size PE array. The algorithm has an improved execution time of O(/spl lceil/m/a/spl rceil/n) required to perform the matching where in, a and n are the sizes of the pattern tree, processor array, subject tree respectively. A prototype CMOS VLSI chip implementing the proposed algorithm has been designed and verified It is shown that the hardware algorithm proposed in this work represent a significant improvement in terms of computational complexity, data flow, and architecture over the ones previously proposed for this problem.

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We propose a novel, high-speed, low-area architecture for multiplication and squaring over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ). The proposed architecture is processor array based, which utilizes the most significant bit multiplication algorithm and polynomial basis. A design space exploration to optimize the area and speed of the proposed architecture was done. Our architecture requires only m processing elements as compared to m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /2 for the best previous design. We use NIST-recommended polynomials, which makes our design secure and more suitable for cryptographic engines. The proposed architecture is implemented for m isin {163,283,571} on a Xilinx XC2V4000-6 device to verify its functionality and measure its performance. We achieve a frequency of 264 MHz, which allows the architecture to calculate GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">163</sup> ) multiplication in 640 ns and squaring in 57 ns.