Virtual Qualification of IC Sockets Using Probabilistic Engineering Methods

The influence of electrical and thermal contact resistance on the efficiency of a segmented thermoelectric generator is investigated. We consider 12 different segmented $p$-legs and 12 different segmented $n$-legs, using 8 different $p$-type and 8 different $n$-type thermoelectric materials. For all systems a universal influence of both the electrical and thermal contact resistance is observed on the leg's efficiency, when the systems are analyzed in terms of the contribution of the contact resistance to the total resistance of the leg. The results are compared with the analytical model of Min and Rowe (1992). In order for the efficiency not to decrease more than 20%, the contact electrical resistance should be less than 30% of the total leg resistance for zero thermal contact resistance, while the thermal contact resistance should be less than 20% for zero electrical contact resistance. The universal behavior also allowed the maximum tolerable contact resistance for a segmented system to be found, i.e. the resistance at which a leg of only the high temperature thermoelectric material has the same efficiency as the segmented leg with a contact resistance at the interface. If e.g. segmentation increases the efficiency by 30% then an electrical contact resistance of 30% or a thermal contact resistance of 20% can be tolerated.

The no-insulation (NI) winding method has been widely used in the fabrication of superconducting coils owing to its excellent thermal stability and mechanical stiffness. In the NI coil, there is a charging delay and heat loss due to leakage current. Therefore, the metal insulated (MI) winding method was proposed to reduce the charging delay and the heat loss due to the leakage current and the increased contact resistance by the metal tape. However, it is difficult to quantify the contact resistance between the turns of the coil during the design stage. To resolve this problem, a new winding method, called soldered metal insulation (SMI), was proposed by the authors, and the electrical properties were evaluated in a bath of liquid nitrogen. As a follow-up to the previous research, experimental investigations were conducted in a conduction cooling test apparatus to investigate the electrical and thermal characteristics of the SMI coil below 77 K. The electric contact resistances were evaluated through sudden discharge experiments. Then, the thermal contact resistances were measured using a heater installed on the outer turn of the coil. It is believed that the SMI winding technique can be applied to fabricate rare-earth barium copper oxide (REBCO) coils with predictable electrical and thermal contact resistances.

Different electronic devices are ubiquitous in our daily lives. These devices keep on improving daily, and their evolution contributes to the enrichment of our lives. However, two factors remain, that is, little or no progress at all has been introduced in the field of electronics for a long time. First, the use of a printed circuit board (PCB) to drive electronic-device circuits has not been improved. The PCB remains thick and hard. Second, the PCB is enclosed in a cabinet for finished products. Generally, device engineers and product designers design electronic circuits and cabinets, respectively. In this case, engineers emphasize that they cannot change the circuit size and arrangement of the lead-out wiring, whereas designers insist that they must realize an attractive cabinet beyond the restriction of the circuit designs.To overcome this issue, conformal printing using a soft blanket has attracted much attention as a technique that can form wires/electrodes on objects with complex shapes. Although the cabinets of electronic devices often have a curved surface, printing that uses a soft blanket can simply and easily form patterns on these electronic devices. At least, wires/electrodes can be formed on a cabinet with a complex shape. Among the many printing methods, the screen-printing-based technology is the most practical. The wires/electrodes of various commercially available electronic devices are fabricated using this printing method. Thus, we are developing screen-printing-based conformal-printing techniques such as screen-offset and screen-pad printing.Screen-offset printing involves screen printing onto a blanket made of silicone and transfer printing from the blanket to a substrate [Fig. 1(a)]. In this process, the organic solvents in conductive ink are absorbed by the silicone. Therefore, collapse of the patterns due to cohesion failure during transfer printing can be prevented. In addition, solvent absorption prevents ink from smudging caused by its fluidity, which subsequently means that fine patterns can be formed compared with those obtained using the conventional screen printing. The width of the patterns formed by screen-offset printing can be as fine as 10 µm, whereas the minimum width obtained by screen printing in mass-produced products is approximately 40–50 µm.Furthermore, the surface free-energy of silicone is low, indicating that screen-offset printing can form patterns even on an adhesive. For example, a material sticks to a screen mask when conventional screen printing is employed. Although heat-applied soldering is often employed for electronic-component mounting, non-heated interconnection can be performed by fixing the electronic components on a screen-offset-printed adhesive substrate using an alignment of component and substrate electrodes.Another feature of the screen-offset printing is that the silicone blanket can deform along the shape of a substrate owing to its softness, which indicates that the conductive ink can be transcriptionally formed on the surface of an object with a complex shape. For example, we developed printed wire-bonding techniques using screen-offset printing [Fig. 1(b)]. A 200-µm-thick Si chip with face-up-type electrodes was arranged on a PCB. Using screen-offset printing, the conductive-ink patterns could climb over the cleaved sidewall of the Si chip because silicone can deform along the steric structure. Thus, wiring connections between the PCB pads and Si-chip pads were successfully performed.Furthermore, screen-offset printing can properly form conductive patterns on textiles [Fig. 1(c)]. For example, plain-woven cotton, which is often used for clothes such as shirts, has a bumpy and porous surface, implying that forming wires/electrodes without breaking is very difficult. However, the silicone blanket can deform along the textured surface. In addition, dried ink caused by organic-solvent absorption of the blanket can bridge the air gap. This wiring technique can contribute to the e-textile technology as a platform for wearable electronics.Applying screen-offset printing on a surface with a large step on the order of millimeters is difficult. To overcome this problem, we need to employ a much softer and thicker blanket to drastically deform along the substrate surface. In contrast, screen printing ink onto such a softer blanket becomes difficult. To address this issue, we have developed screen-pad printing, which is composed of the following: (i) screen printing to a normal blanket, (ii) picking ink to a soft pad from the blanket, and (iii) transcriptionally forming ink patterns on a substrate from the pad. Patterns can be formed even on bumpy surfaces with a large step owing to the soft pad, although the number of processes increases.Common objects generally do not have a flat surface but have a complicated shape. We are currently attempting to fabricate such object-sensor devices by forming functional-material patterns using our developed conformal-printing technique. Figure 1

Fatigue reliability design for metal dual inline packages under random vibration based on response surface method

A novel soldering method to evaluate PCB pad cratering for pin-pull testing

Optimizing the compression resistance of low-nickel stainless steel coronary stents using finite element and response surface methodology

A new design of liquid-cooled heat sink by altering the heat sink heat pipe application: Experimental approach and prediction via artificial neural network

The development of integrated circuit (IC) packaging is one of the important factors for the advanced production of the semi-conductor industry. With the recent rise of innovative demand of the production technology, lot of issues had been raised at the manufacturing level especially at back-end production. In order to solve the problem, finite element analysis (FEA) is one of the methods that has been broadly used to evaluate the internal stress of IC package. The performance effect of tetrahedral or hexahedral dominance elements in the meshing stage may lead to the unswerving of FEA results. In such condition, the performance of the element type needs to be analyzed in order to determine which implementation leads to result with higher confident level. This study used the quasi-static simulation of FEA to determine the performance of tetrahedral and hexahedral dominance elements in FEA of IC package strength. The monitored stress was focused on the component levels of IC package, the die and the diepad. The IC package is modelled in three-dimensional case which represented as close as the actual product by simplifying certain parts. The performance evaluation had considered the effect of grid independent study for each of the element type. The maximum stress produced by using the tetrahedral element had been compared with the stress produced by the hexahedral dominance elements. Comparison of the performance showed that the value of the maximum stress produced from hexahedral dominance element was significantly higher at 16% to 40% than the solution obtained from the tetrahedral element. It is found that by using hexahedral element in the finite element analysis, a significant higher value of Von Mises stress is produced, which is more than 505 MPa in diepad. This stress value has been established by previous study within the plastic deformation range and also has good agreement with the physical examination.Â

During the production of thin shell plastic parts by injection molding, warpage depending on the process conditions is often encountered. In this study, efficient minimization of warpage on thin shell plastic parts by integrating finite element (FE) analysis, statistical design of experiment method, response surface methodology (RSM), and genetic algorithm (GA) is investigated. A bus ceiling lamp base is considered as a thin shell plastic part example. To achieve the minimum warpage, optimum process condition parameters are determined. Mold temperature, melt temperature, packing pressure, packing time, and cooling time are considered as process condition parameters. FE analyses are conducted for a combination of process parameters organized using statistical three-level full factorial experimental design. The most important process parameters influencing warpage are determined using FE analysis results based on analysis of variance (ANOVA) method. A predictive response surface model for warpage data is created using RSM. The response surface (RS) model is interfaced with an effective GA to find the optimum process parameter values.

A new approach to integrated circuit (IC) noise modeling using a single current source for the whole area below the IC on a printed circuit board (PCB) is proposed. This approach extends the frequency of application of similar models in the literature by focusing on the current and power injected into the region outside the IC perimeter. A new measurement equipment for IC electromagnetic compatibility tests above 1 GHz is proposed; the printed reverberation board (PRB). A statistical model for characterizing the PRB is presented and confirmed by measurement results. Limitations of the fabricated PRB prototype and possible improvements are discussed. A new random IC model that includes the random properties of the IC noise is introduced. A methodology to extract the IC model by means of the PRB is presented. An active test PCB has been designed and fabricated to verify the feasibility of the modeling and measurement methods. Measurement results corroborated the validity of the new measurement and modeling approaches on one side, and on the other side showed that further studies are required.

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Comprehensive study and optimization of concentrated photovoltaic-thermoelectric considering all contact resistances

The counterfeit parts, e.g. integrated circuits (ICs) and printed circuit boards (PCBs), have shown significant increase over the recent years. However, existing counterfeit detection techniques deal with IC or PCB separately. Hence cannot verify the authenticity of the electronic system as a whole. In this paper, we propose a novel methodology, named CIPA, which concurrently verifies the authenticity of both IC and PCB through extracting the signature pairs generated by ring oscillator (RO) array without/with PCB cavity resonance. Remote authentication is allowable by transmitting CIPA signatures between the verifier and system vendor. CIPA structure has shown insignificant area overhead (0.945% on average), when implemented on a number of benchmarks. Both CIPA and the benchmarks have been implemented on authentic and counterfeit FPGA systems, results giving 100% confidence in detecting counterfeit ones.

The electronic systems we find in almost every product today are implemented using integrated circuits (ICs) mounted on printed circuit boards (PCBs). Developing electronic systems is a challenging task due to complexity and miniaturization. A single IC can contain billions of transistors, which are smaller than ever. As a result more Design-for-Test (DfT) features, so called instruments, are embedded on-chip in modern ICs to handle and monitor various activities. Many defects are handled at IC manufacturing; however, there are many problems occurring after ICs are being mounted on PCBs. In many cases, it is unfortunately not possible to reproduce the problem when the electronic system is taken to a repair shop. These problems are known as No Trouble Found (NTF). One obstacle is the limited access to the on-chip DfT instruments that exist in most ICs. We will discuss access to on-chip DfT instruments through the life-time of electronic systems. We will focus on electronic systems using the IEEE 1687 standard.

This paper reports on a three-dimensional thermal modeling approach for a lithium-ion battery (LIB). The combined effects of the thermal and electrical contact resistances between the current collecting tab of an LIB cell and the lead wire connecting the cell to an external cycler are considered explicitly in addition to the heat generated as a result of electrochemical reactions and ohmic heating in the electrode region of the battery cell. The effect of electrical contact resistance is taken into account when calculating current collecting tab heating, and the effect of thermal contact resistance is included in the heat flux boundary condition at the contact area between the current collecting tab and the lead wire. The three-dimensional thermal modeling is validated by comparing the modeling results with experimental temperature distributions from IR images during discharge in an LIB cell.