VLSI architectures for DSP applications: current trends

Finite impulse response (FIR) digital filters are key components used in many digital signal processing (DSP) systems because of their linear phase, stability, fewer finite precision errors and regular structure. The real time realization of FIR filter with less hardware requirement and less latency has become very critical with increasing developments in very large scale integration (VLSI) technology. The objective of this paper to explore the current trends in the development of algorithms and architectures for memory based realization of FIR filters that are mainly concerned with reducing the overall area-delay-power complexities. The purpose of this study is to compare these architectures based on ROM size, delay and throughput. The results presented here would assist the researchers in the field of Digital Signal processing to select best architecture for an application based on requirements. New algorithms and architectures need to be developed to design area-delay-power-efficient FIR filters for various demanding DSP applications.

Today, DAW (Digital Audio Workstation) software lies at the heart of music production and has become an indispensable part of the industry. With the advancement of technology, music production is no longer confined to large studios but has also become accessible to individual users. Now, recording, mixing, and mastering processes can be carried out in a home environment using computer-based systems, without the need for expensive equipment. This fully digital workflow is referred to as "in-the-box" production. Technological developments have enabled individuals to produce music at a professional level in home studios, leading to the emergence of digital alternatives to analog devices. Digital processors have begun to replace analog equipment due to their cost-effectiveness and practicality. This study examines the differences between digital signal processors and analog devices in terms of usage, application areas, and sound processing methods. The research aims to compare digital and analog signal processors, particularly focusing on their processing methods, speed, flexibility, quality, and impact on sound. Based on the findings, it is concluded that digital signal processors, which are increasingly replacing analog processors in the music industry, do not possess the same characteristics as their analog counterparts.

A lot of modern ultrasonic measurement (UM) applications use digital signal processing (DSP). In many cases DSP comprises a significant part of system hardware and cost, also it sets certain restrictions on measurement speed and signal-to-noise ratio. This paper deals with the influence of the DSP into signal-to-noise ratio and its relevant characteristicsIt presents a concept of DSP exploration in applications. According to this concept the integrated model UM application - DSP architecture is used to select the rational DSP following the application requirements. The exploration is illustrated with the correlational time delay estimation task. The exploration method was suggested and applied in two scientific projects that have done by Ultrasound Research Center and DSP Laboratory at Kaunas University of Technology. During these projects the ultrasonic vision system for mobile robot (project INCO-COPERNICUS No. ERB IC15-CT96-0726) and high precision ultrasonic gas flowmeter have been designed. In both cases signal processing was necessary and the DSP design presented quite serious problem. The model is implemented in software and provides high flexibility. It can be modified for different DSP methods and signals, therefore, it is applicable for the design of various systems.

The development of modern technologies has fundamentally transformed the field of radar signal and data processing. With the use of advanced algorithms and computational power, radars are now capable of extracting crucial information from received signals, facilitating improved target identification and tracking. This article presents some of the advanced technologies employed in radar signal and data processing and their impact on adaptability of radar systems. It traces the evolution of radar technology from old systems to the present, emphasizing the benefits of adaptive radar signal processing, which includes algorithms such as adaptive beamforming, Space-Time Adaptive Processing, and the integration of Machine Learning and Artificial Intelligence. In conclusion, challenges, and future prospects in the field of radar systems are discussed, with a focus on the potential integration of Artificial Intelligence methods, Cognitive radars, and Multiple Input Multiple Output technologies. Despite technical obstacles, opportunities emerge to enhance the performance of radar systems and achieve new levels of efficiency.

While inverters currently do exist, the main focus of this investigation is to provide a DSP based design that will significantly reduce the cost of the current system. The proposed approach relies on an efficient pushpull DC-DC converter, a digital signal processor (DSP) control mechanism for the DC-AC conversion, and a rigorous cost reduction approach for this inverter. A low cost Texas Instruments, TMS320LF2407 DSP provides the control for the DC-AC converter allowing compliance to the total harmonic distortion (THD) specification of less that 5%. Moreover, the DSP allows convenient communication between the fuel cell and the inverter. The results section of this paper presents our laboratory data. A new closed-loop control scheme is also introduced which reduces the distortion caused by non-linear loads.

This paper traces the development of three-phase induction motor controls using the Semikron advanced integration (SKAI) power electronics system. The SKAI was developed for hybrid and electric vehicles and integrates all the components of a three-phase inverter. As such, it promises to deliver significant cost savings. The SKAI utilizes a digital signal processor (DSP) controller. However, Semikron does not supply the necessary software for the DSP controller. The DSP used in the controller is manufactured by Texas Instruments. Texas Instruments provides an array of DSP programming utilities. This paper discusses aspects of programming and testing the DSP controller

Over the past decade, real time digital signal processing (DSP) has found several new applications in the biomedical arena. One of these has been in the area of hearing aids. This paper presents quantization analysis of speech processing algorithms, for the hearing impaired, for implementation on Texas Instruments' (TI) TMS320C54x (C54x) fixed point DSP chip. These algorithms were initial implemented on TI's floating-point processor, the TMS320C3x (C3x). Portable C3x units were tested on hearing impaired subjects to assure the efficacy of the various speech processing algorithms. The algorithms that proved successful are currently being ported to the CS4x since this chip is being rapidly reduced in size and is on track to be an extremely low power DSP chip, ideal for eventual use in a behind the ear (BTE) or in the ear (lTE) hearing aid.

A fast, power-efficient electro-optical vector-by-matrix multiplier (VMM) architecture is presented. Careful design of an electrical unit supporting high-speed data transfer enables this architecture to overcome bottlenecks encountered by previous VMM architectures. Based on the proposed architecture, we present an electro-optical digital signal processing (DSP) coprocessor that can achieve a significant speedup of 2-3 orders of magnitude over existing DSP technologies and execute more than 16 teraflops. We show that it is feasible to implement the system using off-the-shelf components, analyze the performance of the architecture with respect to primitive DSP operations, and detail the use of the new architecture for several DSP applications.

This paper presents an architecture that combines VLIW (very long instruction word) processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of signal processing applications. To support this architecture, a compilation and design automation flow is described for algorithms written in C. The key contributions of this paper are as follows: (1) a 4-way VLIW processor implemented in an FPGA, (2) large speedups through hardware functions, (3) a hardware/software interface with zero overhead, (4) a design methodology for implementing signal processing applications on this architecture, (5) tractable design automation techniques for extracting and synthesizing hardware functions. Several design tradeoffs for the architecture were examined including the number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply-accumulate operations. Using the MediaBench benchmark suite, we tested our methodology and architecture to accelerate software. Our combined VLIW processor with hardware functions was compared to that of software executing on a RISC processor, specifically the soft core embedded NIOS II processor. For software kernels converted into hardware functions, we show a hardware performance multiplier of up to times that of software with an average times faster. For the entire application in which only a portion of the software is converted to hardware, the performance improvement is as much as 30X times faster than the nonaccelerated application, with a 12X improvement on average.

Real-time systems are those systems in which the correctness of the system depends not only on the logical results of computation but also on the time at which the results are produced [Stankovic 1988]. They span a broad spectrum of complexity from very simple microcontrollers in embedded systems (a microprocessor controlling an automobile engine) to highly sophisticated, complex, and distributed systems (air traffic control for the continental United States). Other real-time systems include command and control systems, process control systems, and multimedia and high-speed communication systems. Some real-time systems are beginning to add expert systems and other AI technology, creating additional requirements and complexities. At least three major trends in the real-time and embedded systems field have had a major impact on its technology: the increased growth and sophistication of embedded systems, the development of more scientific and technological results for hard real-time systems, and the advent of distributed multimedia. Most embedded systems consist of a small microcontroller and limited software situated within some product such as a microwave oven or automobile. However, with the increasing sophistication of such systems, powerful microcontrollers and digital signal processing (DSP) chips are commonly used, as are off-the-shelf real-time operating systems and design and debugging tools. Many people working with embedded systems deal on a daily basis with sensors and data acquisition technology and systems; others construct architectures based on single-board computers (many are still 68000-based, but RISC processors are being used more and more) and buses such as the VME bus. Many people are involved with the programming and debugging of embedded systems, largely using the C programming language and cross development and debugging platforms. Embedded systems may or may not have real-time constraints. Hard real-time systems are those in which missing an important deadline can cause severe consequences, even death. In this area, many fundamental results have been developed. For example, in real-time scheduling, rate monotonic analysis has enabled careful evaluation of many practical systems; the concept and analysis of competitive algorithms has provided important scheduling bounds and limits; and on-line planning has added flexible and dynamic capabilities to real-time systems. Operating systems research has produced predictable primitives, time-constrained synchronization techniques, and reservation and admission-control paradigms. Many other results exist in real-time architecture, fault tolerance, communication protocols, specification and design tools, formal verification, databases and object-oriented systems. Emphasis on all these areas is expected to increase in the foreseeable future. Many hard real-time systems are embedded systems. Distributed multimedia have produced a new set of soft real-time requirements. Real-time principles lie at the heart of distributed multimedia, but without the concomitant high reliability

The traditional methods to implement image processing are either using general programmable digital signal processor (DSP) based instruction or using dedicated signal processing chips. The dedicated chips can deal with tasks they are designed for efficiently, but with others tasks their performance dropped very mich. The general processors have high flexibility but low performance. In many designs, we usually take multi-DSP system to attain the high performance and flexibility but we must face the complex software task on multi-processor system. In this paper, we introduce the concept and advantage of reconfigurable technology. Then we analyzed the real-time requirements of some image-processing algorithms.

In developing a portable device capable of capturing and decoding the two-dimensional MaxiCode symbology, the authors researched and benchmarked several microprocessors. The processor had to be able to quickly execute DSP algorithms, including FFT's and filters. It needed to be small, inexpensive, and have low power consumption. Ease of software development was also a consideration. It may come as a surprise to some that a RISC processor was selected rather than a DSP chip. >

As the flexibility offered by fine-grained field programmable gate array (FPGA) comes at a significant cost of area, speed, and power, there is a trend to use coarse-grained architecture (CGA) for dataflow applications requiring high computational resources. Existing CGA solutions are characterized according to the general organization, the processing element architecture, the basic interconnect structure and their reconfiguration characteristics. Based on the study of several digital signal processing (DSP) applications and their implemented VLSI architectures, we propose a CGA with parameterizable and flexible blocks based on a generic matrix and interconnected by a configurable network. The proposed architecture provides a good tradeoff between flexibility and performance-density. A CAD tool is developed to automate the implementation of the design on the architecture. A synthesizable VHDL code generator is also developed in order to further explore and validate the proposed architecture. The unification of coarse-grained logic block and bus-based interconnection bridges the gap between application-specific integrated circuit (ASIC) and CGA, resulting in area reduction from 40× to 6×, respectively. Experimental results demonstrate the performance and efficiency of the proposed architecture to implement DSP designs.

Nowadays, with the development of space exploration technologies, satellites and other spacecraft have undertaken more important and complicated space science missions, which require powerful processing capabilities to conduct large amounts of probe data real-time processing and analysis. However, the raw data generation rate of space exploration is always far beyond space transmission ability, so orbit compression for original data is an essential technology. Digital Signal Processors (DSPs) with powerful signal processing capabilities have been widely used in various information processing spacecraft systems. However, the utilization of full DSPs’ performance potential depends on parallelism of programs. Based on the C6000, a series of commercial high performance DSP processors, the paper implement the entire discrete wavelet transform module in JPEG2000 image compression algorithm with linear assembly language. Combined with characteristics of DSP instruction sets and features of specific programs, we optimize programs and improve the execution performance by an order of magnitude than previous.

The multimedia SoC usually integrates programmable digital signal processors (DSP) to accelerate data-intensive computations. But the DSP and the host processor (e.g. ARM) are both designed for standalone uses, and they must have overlapped functionalities and thus some redundant components. In this paper, we propose a compact DSP core for dual-core multimedia SoC and its complete software development tools. The DSP core contains a dataflow engine that is composed of off-the-shelf memory modules with limited ports, and we have investigated software techniques extensively to reduce the hardware complexity as the principles of VLIW processors. Moreover, the DSP is equipped with novel static floating-point units to emulate expensive floating-point DSP operations at low cost. In our experiments, this core has about thrice the performance (estimated in execution cycles) of Analog Devices ADSP-218x with similar computing resources. Our first prototype in the 0.35um CMOS technology operates at 100MHz and consumes 122mW power. The core size is 2.8mm2 including an embedded DMA controller and the AMBA AHB interface.