VLSI cellular array of coupled delta-sigma modulators for random analog vector generation

In this work, a secure second-order discrete time delta sigma (ΔΣM) modulator is used to securely modulate two physiological signals for e-health applications. The chaotic system used is a new 3D chaotic system that is used to generate random keys for encryption. Quintic nonlinearity is integrated into the existing sprott chaotic system and then studied via nonlinear dynamics tools, which reveal complex dynamics, including the coexistence of three distinct chaotic attractors and the phenomenon of intermittency. A microcontroller implementation of the system is performed to demonstrate its real-life applicability. The bits generated from the chaotic regime of the proposed oscillator are tested successfully via the NIST-800.22 test. The pseudo random bit streams generated from the chaoticity of the oscillator using the system parameters and initial conditions as secret keys are used in a 2-stage confusion process to encrypt two physiological signals. At the receiving end, the physiological signals are successfully recovered, and some standard metrics, such as key space analysis, key sensitivity, and cross-correlation, are applied to verify the strength of the encryption scheme. A comparison with recent and good standing contributions in the literature is also provide at the end of this work, which shows that the proposed scheme is robust against common attacks. The results obtained in this study open the possibility of applying chaos in digital communication systems for the conception of secure e-health services.p. 2Highlights• A new random chaotic system applicable in information protection is conceived and experimented.• Random encryption data are successfully generated from the chaotic system in its confused state and tested statistically. • Patient's ECG signal is securely transferred via a secure and simple communication scheme.

Chaotic neural networks consisting of a great number of chaotic neurons are able to reproduce the rich dynamics observed in biological nervous systems. In recent years, the memristor has attracted much interest in the efficient implementation of artificial synapses and neurons. This work addresses adaptive synchronization of a class of memristor-based neural chaotic systems using a novel adaptive backstepping approach. A systematic design procedure is presented. Simulation results have demonstrated the effectiveness of the proposed adaptive synchronization method and its potential in practical application of memristive chaotic oscillators in secure communication.

Abstract— A 2.5 V feed-forward second-order delta-sigma modulator for audio application is presented. A 9-level quantizer with a tree-structured dynamic element matching (DEM) was employed to improve the linearity by shaping the distortion resulted from the capacitor mismatch of the feedback digital-to-analog converter (DAC). A chopper stabilization technique (CHS) is used to reduce the flicker noise in the first integrator. The prototype delta-sigma analog-to-digital converter (ADC) implemented in a 65 nm 1P8M CMOS process occupies 0.747 mm 2 and achieves 109.1 dB dynamic range (DR), 85.4 dB signal-to-noise ratio (SNR) in a 24 kHz audio signal bandwidth, while consuming 14.75 mW from a 2.5 V supply. Index Terms —Delta-sigma modulator, feed-forward, dynamic element matching, chopper stabilization I. I NTRODUCTION Recent advances of CMOS technology have enabled the high quality signal processing in the multi-media and communication systems and have resulted in a great demand for the high resolution analog-to-digital converters (ADCs). Among various ADC architectures, the delta-sigma ADC offers high dynamic range by using oversampling and noise shaping properties. Moreover, as it requires only simple and relatively high-tolerance analog components with fast and complex digital signal processing to achieve high resolution, it is very well-suited for the digital CMOS process. The theoretical signal-to-quantization noise ratio (SQNR) of the delta-sigma ADC is given by Eq. (1)

Design techniques for IIR filters operating on oversampled delta-sigma ( Delta Sigma ) modulated signals are presented. It is shown that Delta Sigma -based IIR filters can be efficiently realized by eliminating all multibit multipliers through the use of remodulating internal filter states. Noise results are presented showing that linear noise analysis gives excellent predictions of the noise performance over the frequency band of interest. It is also shown that latency and computational complexity can be reduced in some VLSI applications where digital representations of analog signals exist using oversampled Delta Sigma converters. >

Copulas are used in finance and insurance for modeling stochastic dependency. They comprehend the entire dependence structure, not only the correlations. Here they are estimated from measured samples of random vectors. The copula and the marginal distributions of the vector elements define a multivariate distribution of the sample which can be used to generate random vectors with this distribution. This can be applied as well to time series. A programmed algorithm is proposed. It is fast and allows for random vectors with high dimension, for example 100.

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With the development of science and technology, Sigma-Delta (∑-A) ADCs are widely used in various fields of electronics with their flexible advantages. As an essential component of a Sigma-Delta ADC, digital filters directly and significantly impact the ADC's accuracy, delay, and power consumption. This paper presents a multistage digital filter for 18-bit ∑-A ADCs; the filter uses a cascade of multiple filters, including cosine-like (CL), cascaded integral comb (CIC), interpolated second-order polynomial (ISOP), and half-band (HB) filters, to enhance the ADC's accuracy. The filter's order and downsampling multiplier are designed using canonical signed digit (CSD) and common subexpression (CSE) to reduce hardware resource consumption and improve computational performance. The ADC is synthesized using 0.18 µm CMOS technology, achieving an output SNDR of 96.26 dB, ENOB of 15.73 bits, total power of 518.35 uW, and a Digital filter power of 82.93 uW, which effectively reduces the power consumption while improving the accuracy.

Chaos science is also used in the fields of medicine, biology and finance besides in the engineering fields such as communications, electronics and computer. Up till today, many different chaotic systems have been introduced in the literature in order to be used in these fields. The majority of these systems have usually been examined numerically and only some of them have electronic circuit design. The chaotic systems must be able to be done electronically especially in the fields such as secure communication, encryption, etc. In 1994 were found 19 attractor systems that were simple-structured but producing complex chaotic signals and named A to S by Sprott. In this study electronic circuit design of Sprott H chaotic system with the positive (non-inverting) second generation current conveyor with high gain and high bandwidth were performed in Orcad-PSPICE program. Numerical analysis results of Sprott H chaotic system and the designed electronic circuit outputs were found to be the same. The system can be used secure communication and encryption applications of which electronic circuit were designed.

A 1-V low-power 2.4-GHz fractional-N frequency synthesizer with sigma-delta modulator controller for Bluetooth applications is implemented in 0.18 /spl mu/m CMOS technology. A novel structure dual-modulus divide-by-128/129 prescaler using a dynamic D-flip-flop is proposed and the operating clock frequency can reach as high as 2.6 GHz at 1-V supply voltage. Moreover, a third-order feedforward sigma-delta modulator (SDM) is employed as a modulus controller to achieve an appropriate division ratio and suppress the fractional spurs. Simulation results show the synthesizer possesses a tuning range of 2.136 to 2.53 GHz and a phase noise of -126.85 dBc/Hz at 1 MHz offset. Moreover, the core area without the SDM and the loop filter is 0.85 mm/sup 2/, and the total power consumption is 8.94 mW.

The rapid scaling in modern CMOS technology has motivated the researchers to design new analog-to-digital converter (ADC) architectures that can properly work in lower supply voltage. An exchanging the data quantization procedure from the amplitude to the time domain, can be a promising alternative well adapt with the technology scaling. This paper is going to review the recent development in time-based noise-shaping ADCs, so-called as time-based sigma-delta modulators. Two of the most important architectures named as voltage-controlled oscillator (VCO) -based and time-to-digital (TDC) -based sigma-delta modulators (SDMs) are selected to be reviewed in this paper. The intrinsic advantages and limitations of the these structures are briefly explored. To confirm the effectiveness of the time-mode sigma-delta modulators, a TDC-based continuous-time sigma-delta modulator is proposed as an example and the related simulation results performed in MATLAB are illustrated. The simulation results show that the proposed modulator achieves a dynamic range of 67 dB over 30 MHz with the loop filter of order 2. The proposed TDC-based sigma-delta modulator shows the superiority of the time quantization approach in designing the wideband and less complex continuous-time SDMs.

A fast symbolic SNR computation method and its Verilog-A implementation for Sigma-Delta modulator design optimization

Recently, a new six-term 3-D chaotic system with an exponential nonlinearity was discovered (Sundarapandian, 2013). This novel chaotic system has two saddle focus nodes and hence they are unstable. The maximal Lyapunov exponent (MLE) for the six-term Sundarapandian chaotic system was found as 3.2827 and the Lyapunov dimension of the Sundarapandian chaotic system was found as D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> = 2.1668. Complete synchronization of chaotic systems deals with the problem of asymptotically synchronizing the states of a pair of chaotic systems called as master and slave systems with the help of controllers attached to the slave system. Complete synchronization of chaotic systems has applications in many engineering areas such as secure communications, secure data encryption, cryptosystems, etc. This paper addresses the design of active and adaptive feedback controllers for completely synchronizing the states of identical six-term Sundarapandian chaotic systems with exponential nonlinearity. Active controllers are used when the system parameters a, b and c are available for measurement and the synchronization result is established using Lyapunov stability theory. Numerical simulations using MATLAB have been shown to demonstrate the proposed active and adaptive synchronization results for the novel chaotic system discussed in this paper.

The main contribution of this paper is to propose a nonlinear robust controller to synchronize general chaotic systems, such that the controller does not need the information of the chaotic system’s model. Following this purpose, in this paper, two methods are proposed to synchronize general forms of chaotic systems with application in secure communication. The first method uses radial basis function neural network (RBFNN) as a controller. All the parameters of the RBFNN are derived and optimized via particle swarm optimization (PSO) algorithm and genetic algorithm (GA). In order to increase the robustness of the controller, in the second method, an integral term is added to the RBF neural network gives an integral RBFNN (IRBFNN). The coefficients of the integral term and the parameters of IRBFNN are also derived and optimized via PSO and GA. The proposed methods are applied to the famous Lorenz chaotic system for secure communication. The performance and control effort of the proposed methods are compared with the recently proposed PID controller optimized via GA. Simulation results show the superiority of the proposed methods in comparison to the recent one in improving synchronization while using smaller control effort.

In this paper, a secure communication is proposed based on synchronisation between nonidentical (topologically non-equivalent) chaotic systems. A drive-response philosophy is used where one chaotic system is used as transmitter and other chaotic system with controller is used as a receiver. A nonlinear active control (NAC) scheme is designed to achieve synchronisation between nonidentical chaotic systems with application to secure communication. Controller is designed by using sum of the relevant variables of the drive and response systems. Required stability condition is derived based on Lyapunov stability theory. MATLAB simulation is used for the effective verification of the proposed scheme. Simulation results reveal the successful achievement of the proposed concept of secure communication.

Recurrent neural networks-guided vector-valued synchronized key exchange for secure and privacy-preserving communication in Industrial Internet of Things