VLSI Circuit Analysis, Timing Verification and Optimization

This paper presents a simulation technique and a computer program for fast DC analysis of MOS transistor based VLSI circuits. Time domain analysis of a VLSI circuit is evaluated by a piecewise constant waveform approximation. This approximation is realized by repeatedly applying the developed DC analysis engine with initial conditions. All proposed methods such as device modeling, circuit partitioning and event-driven simulation were implemented and combined with such well known algorithms as modified nodal analysis (MNA), Katzenelson algorithm and Gaussian elimination in the form of a circuit simulation program: SAMOC. Time domain waveforms and benchmark circuit simulation results comparison of SPICE and SAMOC are presented.

Considerable attention has been given to automating the design of electronic circuits during the last decade. The principal areas of research and development include: (1) simulation, timing verification and fault modeling, (2) placement, routing and partitioning, (3) silicon compilers, and (4) hardware description languages. Computer-aided-design systems have been recently introduced based on the above research. Techniques have also been developed for mapping numerical algorithms onto highly parallel architectures that are well suited for fabrication as VLSI/VHSIC chip sets. Design rule checkers may also be used to verify that a design meets a specified set of physical implementation constraints prior to fabrication. In this paper, these hardware design automation techniques will be surveyed to determine the state-of-the-art in this important area of computer-aided-design.

This paper describes a linear programming (LP) problem formulation applicable to the static-timing analysis of large scale synchronous circuits with level-sensitive latches. Specifically, an LP formulation for the clock period minimization problem is developed. In order to minimize the clock period of level-sensitive circuits, the simultaneous effects of time borrowing and nonzero clock skew scheduling are considered. The clock period minimization problem is formulated for both single-phase and multi-phase clocking schemes. The ISCAS'89 benchmark circuits are used to derive experimental results. LP minimization problems for these benchmark circuits are generated using the modified big M (MBM) method and the generated problems are solved using the industrial LP solver CPLEX . The experimental results demonstrate up to 63% improvements in minimum clock period compared to flip-flop based circuits with zero clock skew.

Carbon nanotube field-effect transistors (CNFETs) show great potential to build digital systems on advanced technology nodes with big benefits in terms of power, performance, and area (PPA). However, CNFET-specific additional features such as the number of tubes, pitch (spacing between tubes), tube position, and diameter in array of tubes play a significant role in accurate PPA evaluation. Furthermore, count and density variations in carbon nanotubes (CNTs) due to manufacturing limitations, like the presence of metallic tubes in the CNFET channel, degrade the anticipated PPA benefits. Moreover, modeling the CNFET parameters, CNT variations and etching techniques for CNTs create additional complexity during performance optimization. Hence, for realistic optimization of CNFET circuit’s performance, it is imperative to incorporate the impact of these parameters and variations. In this paper, we propose delay models [pitch-aware logical effort (PALE) and position-aware pitch factor (PAPF)] for fast and accurate performance evaluation by including the impact due to CNFET-specific parameters and CNT variations. These models are developed based on industry standard logical effort framework. Furthermore, we present an optimization tool using PALE and PAPF to minimize the delay and area of CNFET circuits. We deploy several circuit-level techniques prior to optimizing the tubes (CNTs) in the logic gates to achieve globally optimum solution. For better optimization of the circuits, we also include the impact of wire parasitic in estimating the delay of the individual gates. Our optimization tool results in the maximum and average delay improvement by 27% and 17%, respectively, and $2.5\times $ reduction in area for standard ISCAS and OpenSPARC benchmark circuits. Fast and fairly accurate delay computation in our optimization framework offers great runtime benefits as compared to state-of-the-art simulation and statistical-based methods.

The authors describe a circuit simulation, analysis and optimization software which can utilize the most common parallel processing hardware, i.e. the workstation network. The parallel processing ability has been implemented using an easy-to-use but powerful methodology. The efficiency of this methodology is demonstrated in terms of both CPU and programmer time. The feasibility of converting even large existing software systems for at least partial parallel execution is demonstrated. With a suitable set of tools the amount of changes which are needed is small. Despite the limited bandwidth of an Ethernet network, a set of networked computers can be used as an efficient parallel processor for some of the problems in electronic design automation. >

Several methods have been developed for the analysis of circuits with periodically switched linear networks. One of the earlier works, published in the 1950s, performed the analysis of these networks using a state-space methodology based on unit complex sinusoidal step responses and unit relaxation functions, for the different switch states [1]. In the 1970s, other methods were published, using different approaches of the same methodology, which were more suitable for digital computation [2, 3]. In [4], the state-space methodology was adapted specifically for switched-capacitor (SC) circuits, which led to significant simplifications, due to the reduced number of different elements. In [5], a more computationally efficient state-space analysis method, valid for any ideal switch configuration, was presented.

The computation time required for the analysis and optimization of a complete circuit can be too long. The use of symbolic analysis together with model order reduction techniques can reduce it and make the optimization a practicable way in the circuit design. To evaluate the possibilities offered by the technique, firstly a linear test case has been considered. The problem of an inductor simulation has been analyzed by introducing simplified analytical expressions and different optimization algorithms in the fitting/optimization process. Then the optimization technique has been applied to a real circuit, a voltage reference, trying to improve the stability of the reference over the temperature.

We present a symbolic simulation based verification approach which can be applied to large synchronous circuits. A new technique to encode the state and input constraints as parametric Boolean expressions over the state and input variables is used to make our symbolic simulation based verification approach efficient. The constraints which are encoded through parametric Boolean expressions can involve the Boolean connectives (·, +, ⌝), the relational operators (<, ≤, >, ≥, ≠, =), and logical connectives (∧, ∨). This technique of using parametric Boolean expressions vastly reduces the number of symbolic simulation vectors and the time for verification. Our verification approach can also be applied for efficient modular verification of large designs; the technique used is to verify each constituent sub-module separately, however in the context of the overall design. Since regular arrays are part of many large designs, we have developed an approach for the verification of regular arrays which combines formal verification at the high level and symbolic simulation at the low level(e.g., switch-level). We show the verification of a circuit called Minmax, a pipelined cache memory system, and an LRU array implementation of the least recently used block replacement policy, to illustrate our verification approach. The experimental results are obtained using the COSMOS symbolic simulator.

Most existing buffering algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches considering inductance effects, their delay models are too simplistic to catch the actual performance. As delay-length dependence is approaching linear with inductance effect (Ismail and Friedman, 1999), fewer buffers are needed to reduce RLC delay. This motivates this work to propose a new algorithm for RLC buffer insertion. In this paper, a new buffer insertion algorithm considering inductance for intermediate and global interconnect is proposed, based on downstream impedance instead of traditional downstream capacitance. A new pruning technique that provides tremendous speedup and a new frequency estimation method that is very accurate in delay computation are also proposed. Experiments on industrial netlists demonstrate that our new algorithm reduces the number of buffers up to 34.4% over the traditional van Ginneken's algorithm that ignores inductance. Our impedance delay estimation is very accurate compared to SPICE simulations, with only 10% error while the delay model used in the previous RLC algorithm has 20% error (Ismael et al., 2001). The accurate delay model not only reduces the number of buffers, but also brings high fidelity to the buffer solutions. Incorporating slew constraints, the algorithm is accelerated by about 4times with only slight degradation in solution quality

The problem of the symbolic analysis of nonlinear dynamical behaviour in the design of analogue circuits and systems is addressed in this paper. Where classical circuit and system level simulators basically rely on numerical simulations for that analysis, a symbolical method is considered here. This method is based on the Volterra Series (VS). A short introduction on the use of VS in system analysis is given. An implementation of a symbolic system analysis tool in its first stages based on VS is described. Complexity and efficiency of the implemented methods are discussed. An example is given where the implemented analysis tool is used optimise a simple circuit. The results are verified with Spice. Finally, an outlook on the open problems of the current implementation is given.

Integrated Gate Commutated Thyristors (IGCT) has a natural advantage in high voltage and large capacity power electronic equipment due to its high current processing capability. However, due to the positive feedback in the IGCT turn on process, the turn-on clamp circuit must be added to limit the switching speed which reduces system efficiency. This paper firstly introduces the working principle of opening clamp circuit. Secondly, the bus current in Modular Multilevel Converter (MMC) and Double Active Bridge (DAB) are compared, and pointed that the backflow power of DAB will significantly increase the loss of clamped circuit. In order to reduce the loss if clamped circuit and further improve the efficiency of IGCT-DAB, reducing the inductance and buffer capacitor in parallel with the IGCT were proposed, and their feasibility was analyzed. Finally, a DAB prototype of 1.5kV/3MW was constructed in MATLAB/Simulink to verify the correctness of the theory.

A new CAD approach for analysis, development, and optimization of millimeter-wave oscillator circuits is presented. The method has been developed with respect to universality, accuracy, and efficiency regarding the consistent modelling of active two-terminal devices operating in passive circuits. Some benefits of the approach are demonstrated by a number of results for practically realized Si and GaAs CW IMPATT oscillators at 94 and 140 GHz. It is likely that millimeter-wave IMPATT diodes operate often in a subharmonic mode in which the fundamental power may or may not be reduced compared to a single-frequency excitation.

Multi-objective optimization and analysis of divided-layer varying-network magnetic circuit based axial field flux-switching magnetic gear composite motors

It is widely believed that any true (or sensitizable) critical path of length /spl ges/2 T must be speeded up in order for a circuit to have a delay <T. I demonstrate that this notion is pessimistic. Many true paths can never affect the delay of the circuit-whenever such a path propagates a signal, some other path that is at least as long also propagates a signal. The theory for a new classification of paths based on the impact on the circuit delay is presented and conditions are given under which a path (or a set of paths) must be speeded up in order to improve the circuit delay. The conditions for the categorization are independent of the delays in the circuit and are valid for all delay assignments. This work indicates that the widely employed notions of true and false paths may be misleading both for timing optimization and delay analysis of logic circuits.

This paper proposes the use of Karhunen-Loève Expansion (KLE) for accurate and efficient modeling of intra-die correlations in the semiconductor manufacturing process. We demonstrate that the KLE provides a significantly more accurate representation of the underlying stochastic process compared to the traditional approach of dividing the layout into grids and applying Principal Component Analysis (PCA). By comparing the results of leakage analysis using both KLE and the existing approaches, we show that using KLE can provide up to 4-5x reduction in the variability space (number of random variables) while maintaining the same accuracy. We also propose an efficient leakage minimization algorithm that maximizes the leakage yield while satisfying probabilistic constraints on the delay.