VLSI Implementation of High Performance RSA Algorithm Using Vedic Mathematics

The discrete multitone (DMT) modulation/demodulation scheme is the standard transmission technique in the application of asymmetric digital subscriber lines (ADSL) and very-high-speed digital subsc...

The requirement for an automated test system has immensely increased due to the realization that manual testing is associated with additional resources and staffing constraints. In order to achieve a competitive edge, reduced development cost, timely product delivery, and product quality are mandatory in today's organization. Manual testing requires skilled operators that increase cost, time, and product delivery. The low cost computer based automated system helps to get an edge by fulfilling these organizational demands. In this paper, an automated testing system has been developed to support functional testing of Nortel Network's modem system (1-Meg SUT). The modem is an inherently complex asymmetric digital subscriber line (ADSL) product and its testing is far more complex than just verification of process faults. The complexity of ADSL system renders automated test system an important and imperative part of ADSL testing. The subject paper demonstrates the indispensable need of automated test system for ADSL testing and its advantages in providing a competitive edge for the organization.

Time-domain equalization is crucial in reducing channel dispersion and canceling interference in multicarrier systems. The equalizer is a finite impulse response (FIR) filter with the purpose that the delay spread of the combined channel-plus-equalizer IR is not longer than the cyclic prefix length. In this paper, a specific framework of long FIR channel-shortening problem is studied. In fact, approximated by a stable pole-zero model, we show that the channel transfer function poles introduce interference. Hence, to cancel bad poles, we propose the use of lattice structure to implement the channel shortener which places their zeros very close to critical channel poles and cancels them out. For low complexity implementation, we adopt adaptive algorithms to design the lattice channel shorteners. This paper analyzes the lattice structure performances of two blind adaptive channel shorteners: sum-squared autocorrelation minimization and multicarrier equalization by restoration of redundancy algorithms. The proposed implementation performances are given in terms of bit rate, and the simulation results are studied in the context of asymmetric digital subscriber line system.

Multi-carrier modulations have generated strong interest recently because of the challenging characteristics of important contemporary channels. While the idea of partitioning spectrally using orthogonal frequency division multiplexing (OFDM) was developed over thirty years ago, its implementation as a practical solution to a communications system problem is much more recent due to advances in digital signal processing and VLSI. Implementation has brought about a simultaneous increase in developing analysis that allow the performance characteristics of the approach to be understood in practical channels. Example channels where OFDM is being strongly considered are data communications over CATV channels and wireless applications such as digital terrestrial broadcasting. Widespread consideration of OFDM as a primary transport mechanism has occurred to date only for high speed data over the twisted pair channel. In this application, the technology is referred to as the Asymmetric Digital Subscriber Line (ADSL). Unlike that application, however, CATV and wireless systems represent RF channels. As such, one important characteristic of each is the phase jittery nature of low-cost, high frequency synthesized carriers. The research will present unique results indicating how these impairments degrade the OFDM system. The approach taken is to model the untracked jitter variation as a lowpass process, note the breakdown of traditional assumptions associated with single carrier modulations, and proceed with analytical solutions from this practical model. The single carrier solutions required are developed, including solutions for slow and rapid phase noise for standard and offset 16-QAM. Results for 64-QAM are also developed, and can be easily extended to any rectangular constellation, such as 256-QAM or 1024-QAM. A comparison of the various simplifying analysis assumptions is made to contrast with exact performance curves when phase noisy RF channels are encountered. A straightforward technique to improve link margin on phase-noise limited, slow jitter channels is presented. Finally, system design guidelines are developed for the difficult moderately varying jitter situation, critical for multi-carrier systems that rely on multiple subchannels of individually low symbol rate.

Orthogonal frequency division multiplexing (OFDM) is a multicarrier modulation used in a variety of broadband systems, such as asymmetric digital subscriber lines, very-high-speed digital subscriber lines, digital video and audio broadcasting, and wide local area network standards. OFDM is a promising solution achieving high data rates in a mobile environment. In wireless communication systems, signal distortion and attenuation in transmission caused by multipath effects makes it necessary to obtain knowledge related to the channel impulse response using channel estimation to provide compensation. This study combined a back propagation neural network for the estimation of channel and compensation signals with a genetic algorithm to improve performance and the convergence rate. We compared bit error rates and the mean square error of the proposed neural network with that of the conventional neural network, the least square (LS) algorithm, and the minimum mean square error (MMSE) algorithm in existing OFDM channel environments. Our results demonstrate that the proposed algorithm outperforms the LS algorithm and is on par with the MMSE algorithm.

System-on-a-chip (SoC) is now a trend in digital design because it gives a lot of advantages over discrete electronic based product such as higher speed, lower power consumption, smaller size, lower cost etc. Reconfigurable platforms such as FPGA, CPLD, and PLD are now being used for designing and implementing SoC due to their low cost, high capacity and tremendous speed. In this project single chip Orthogonal Frequency Division Multiplexing (OFDM) transmitter and receiver have been designed using Verilog HDL. OFDM is a multi carrier modulation technique used in the various digital communication systems like 3G GSM, WiMAX and LTE etc. The main advantage of this transmission technique is its robustness to channel fading in wireless communication environment. There are many applications of OFDM in communication such as digital audio broadcasting, Asynchronous Digital Subscriber Line (ADSL) and High bit-rate Digital Subscriber Line (HDSL) systems. In OFDM, two algorithms digital signal processing algorithm Fast Fourier transform (FFT) and Inverse Fast Fourier Transform (IFFT) are mainly involved. The 8-point IFFT/FFT Decimation-In-Frequency (DIF) with radix-2 algorithm has been analyzed and incorporated in the design. The design has been simulated on the FPGA platform with Altera's Quartus II simulator. Simulation results show that each of the modules of the proposed OFDM is working as desired. The test output achieved from the simulation result of the OFDM has been verified with that of the MATLAB output.

Over the past three decades, the scientific and industrial communities have injected considerable resources into perfecting orthogonal frequency division multiplex (OFDM) - the driving technology behind many applications used today (such as IEEE 802.11g, asymmetric digital subscriber line (ADSL), and digital terrestrial television). In 1997, OFDM was officially sanctioned for use in the European Telecommunications Standards Institute (ETSI) EN 300 744 standard known as digital video broadcasting-terrestrial (DVB-T). As OFDM is such a popular technology, there has been limited research over the years into alternatives. This paper proposes a novel approach to transmit parallel information through a terrestrial channel that could render it a more flexible alternative to OFDM in the future. Investigations have shown that this technique could provide a highly flexible, channel optimized modulation technique based on time-frequency multiplexing and this paper presents the preliminary phase of investigations into this new technique .

A computationally efficient optimal discrete bit allocation algorithm is proposed for medium and high target bit rate discrete multitone (DMT) transmissions. Unlike conventional greedy bit-loading algorithms, which compare the incremental transmission power of multicarriers bit-by-bit and allocate one bit at a time, the proposed algorithm is based on parallel bit-loading with reference to a virtual equal power assignment bit allocation. After maximum bit rate allocation, the algorithm achieves the target bit rate by two types of parallel bit- loading. If the target bit rate allocation is not optimal, bit swapping is performed to obtain the optimal solution. Simulation results using the standard asymmetric digital subscriber line (ADSL) test loops demonstrate the reduced computational load of the proposed algorithm compared to the existing optimal discrete bit allocation algorithm when the target rate is between 60% and 99% of the loop's maximum bit rate.

The transmission of high-speed data over severely band-limited channels may be accomplished through the use of discrete multitone (DMT) modulation, a modulation technique that has been proposed for a number of new applications. While the performance of a DMT system has been analyzed by a number of authors, these analyses ignore the effect of timing jitter on system performance. Timing jitter becomes an increasingly important concern as higher data rates are supported and larger constellations are allowed on the DMT subchannels. Hence, in this paper, we assume that synchronization is maintained by using a digital phase-locked loop to track a pilot carrier, Given this model, we derive error rate expressions for an uncoded DMT system operating in the presence of timing jitter, and we derive an expression for the interchannel distortion that results from a varying timing offset across the DMT symbol. In addition, we investigate the performance of trellis-coded DMT modulation in the presence of timing jitter. Practical examples from the asymmetric digital subscriber line (ADSL) service are used to illustrate various results.

In this paper the general ADSL (asymmetric digital subscriber line) noise environment is reviewed in the context of the telephone loop plant. Special attention is given to the unique unidirectional transmission nature of ADSL. A set of noise environments is presented for related computer simulation studies and hardware tests. A set of mid-CSA test loops is also proposed for performance evaluation under conditions of T1 NEXT interference. To simplify calibration procedures, noise and loop models are revealed in FIR (finite impulse response) filter form and can be measured in dB loss or dBm/Hz power density terms. A subchannel signal to noise ratio (SNR) based computer simulation method is then used to estimate potential ADSL performance under different noise environments for different serving areas. >

In this paper, we investigate the ultimate performance limits, in terms of achievable information rate (IR), of communication systems impaired by impulse noise. We compare single carrier (SC) and multi-carrier (MC) transmission systems employing quadrature amplitude modulation (QAM) formats. More precisely, we consider SC schemes with coded modulations and MC systems based on orthogonal frequency division modulation (OFDM). For the MC schemes, we introduce a theoretically equivalent channel model which makes the computation of the IR feasible. This simple channel model will be referred to as interleaved MC. We show that, in the presence of impulse noise and except for systems operating at very high spectral efficiency, the IR of MC schemes is lower than that of SC schemes. More precisely, use of MC schemes may lead to an unavoidable fundamental loss with respect to SC schemes at typical coding rates, whereas MC schemes are to be preferred for very high coding rates or in uncoded systems. These results hold for additive white Gaussian noise (AWGN) and dispersive channels, either considering plain OFDM or MC schemes employing water-filling and bit-loading algorithms. In order to validate our theoretical results, we also obtain the bit error rate (BER) performance of SC and MC schemes through Monte Carlo simulations. A few trellis-coded modulation (TCM) and low-density parity-check (LDPC)-coded schemes are considered. The obtained SNR loss in the BER curves between the AWGN and impulse noise channels matches well with the corresponding IR gap.

Multicarrier modulation schemes are widely used in several digital telecommunication systems, such as Asymmetric Digital Subscriber Lines (ADSL) and Wireless Local Area Network (WLAN) based on Orthogonal Frequency Domain Multiplexing (OFDM). An estimate of the Bit-Error-Rate (BER) degradation due to non-idealities in the transceiver (e.g. nonlinear distortions in the analog front-ends, digital clipping,...) is much more complicated in a multicarrier system than in a single-carrier system due to the large number of carriers and the huge number of possible transmitted symbols. This paper proposes a method for estimating the BER of such OFDM modulation schemes in a CPU time that is two orders of magnitude smaller than a Monte-Carlo method, as confirmed by simulations on a 5 GHz IEEE 802.11 WLAN receiver front-end.

Multicarrier modulation schemes are widely used in several digital telecommunication systems, such as Asymmetric Digital Subscriber Lines (ADSL) and Wireless Local Area Network (WLAN) based on Orthogonal Frequency Domain Multiplexing (OFDM). An estimate of the Bit-Error-Rate (BER) degradation due to non-idealities in the transceiver (e.g. nonlinear distortions in the analog front-ends, digital clipping,...) is much more complicated in a multicarrier system than in a single-carrier system due to the large number of carriers and the huge number of possible transmitted symbols. This paper proposes a method for estimating the BER of such OFDM modulation schemes in a CPU time that is two orders of magnitude smaller than a Monte-Carlo method, as confirmed by simulations on a 5 GHz IEEE 802.11 WLAN receiver front-end.

This paper presents the design and implementation of novel decimation filter structure for high speed asymmetric digital subscriber line (ADSL). Existing ADSL circuits use comb-FIR-FIR decimation filter structures, which have low throughput, more hardware and high power consumption. Unlike existing ADSL circuits, we design a novel high speed filter architecture and implement it using the minimal signed digit (MSD) representation. The MSD representation is suitable for common subexpression elimination, and it significantly reduces the number of adders required for the filter synthesis. Each digital-filter structure is simulated using Matlab, and its complete architecture is captured using DSP Blockset and Simulink. The resulting filter architecture has higher throughput, less hardware and consumes less power than the comb-FIR-FIR and comb-IIR-FIR architectures. The filter has been implemented on Xilinx FPGA using Virtex-2 technology. Compared to the comb-FIR-FIR and the comb-IIR-FIR architectures, the designed decimation filter architecture contributes to a hardware saving of 82% and 74%, respectively; in addition, it reduces the power dissipation by 91% and 79%, respectively.

The design and optimization of the high-speed digital subscriber line (HDSL) need powerful computational strategies. Traditional techniques of distributing poles and zeros on Smith charts generally do not work. In the past, such approaches have lead to suboptimal designs for applications where the data capacity sought is considerably less than the Shannon capacity of the lines. Typical subscriber loops are less than perfect and for the current demands on the HDSL at T1/T2 and El rates every possible venue for the HDSL design needs to be investigated, if not exploited. In this Chapter, flexible computational techniques are presented that explore and optimize system components in view of the operating environment of the HDSL and/or the asymmetric digital subscriber line (ADSL) and inherent limitations of system components. The optimization occurs automatically by forcing the computer to track the effects of incremental changes of the subsystem performance (e.g., echo cancelers or equalizers), or the component values (Rs and Cs in the matching circuits) in context to the functional constraints of the (HDSL, ADSL, duplex, dual-duplex, triplex, etc.) line in conjunction with various subscriber loop environments (CSA loops, loops <18 kft., American, Australian, European, ANSI, ETSI, etc.)