VML 3.0 Reactive Sequencing Objects and Matrix Math Operations for Attitude Profiling

VML (Virtual Machine Language) is an advanced procedural sequencing language which simplifies spacecraft operations, minimizes uplink product size, and allows autonomous operations aboard a mission without the development of autonomous flight software. The language is a mission-independent, high level, human readable script. It features a rich set of data types (including integers, doubles, and strings), named functions, parameters, IF and WHILE control structures, polymorphism, and on-the-fly creation of spacecraft commands from calculated values. VML has been used on six JPL deep space missions. It is currently in use on Mars Odyssey, Stardust, Genesis, and the Space Infrared Telescope Facility (SIRTF). It is slated for use on the 2005 Mars Reconnaissance Orbiter. The language and associated flight code has allowed spacecraft operations teams to place autonomy aboard deep space missions, implemented as operations products (blocks and sequences). The flight component of VML is implemented in C. This paper lays out language constructs and capabilities, code features, and VML operations development concepts.

An overview of the flight software development for the Ionospheric Observation Nanosatellite Formation (ION-F) is presented. ION-F, a constellation of three 15 kg satellites to be launched from the Space Shuttle in mid-2002, is designed as an experiment in formation flying technologies. The satellites will utilize micro-pulsed plasma thrusters and an integrated GPS/cross-link system to allow fast and accurate update of relative satellite positions. This paper describes the ION-F formation flying mission, flight software development to date, and simulation results. A nonlinear simulation environment (hardware in the loop) has been developed that includes the full nonlinear orbital dynamics in FreeFlyer/sup TM/, and nonlinear attitude dynamics in MATLAB/sup TM/. The simulation allows extensive flight software development to take place by integrating modules developed in C/C++ within the MATLAB environment.

At the Technical University Munich the Institute of Flight System Dynamics uses different manned and unmanned aerial platform to demonstrate modern flight control and flight management functions. Those algorithms are designed, implemented and tested using MATLAB Simulink and Stateflow. The context of high-integrity aircraft controller software claims various limitations of the tools. The state machines used in the flight control software are developed using a special combination of MATLAB Simulink and Stateflow. That can greatly reduce complexity while simultaneously enhancing clarity and testing abilities. This paper contains a detailed explanation of the implementation scheme and structure developed at the Institute of Flight System Dynamics to design multi-level finite state machines in the context of high-integrity aircraft controller software.

Chapter 8 - Hierarchical State Machines

This work is motivated by a particular software reliability problem in a unit of flight control software developed by the Indian Space Research Organization (ISRO), in which the testing of the software is carried out in multiple batches, each consisting of several runs. As the errors are found during the runs within a batch, they are noted, but not debugged immediately; they are debugged only at the end of that particular batch of runs. In this work, we introduce a discrete time model suitable for this type of periodic debugging schedule and describe maximum likelihood estimation for the model parameters. This model is used to estimate the reliability of the software. We also develop a method to determine the additional number of error‐free test runs required for the estimated reliability to achieve a specific target with some high probability. We analyze the test data on the flight control software of ISRO. Copyright © 2011 John Wiley & Sons, Ltd.

Distributed terrestrial computer systems employ middleware software to provide communications abstractions and reduce software interface complexity. Embedded applications are adopting the same approaches, but must make provisions to ensure that hard real-time temporal performance can be maintained. This thesis presents the development and validation of a middleware system tailored to spacecraft flight software development. OurmiddlewarerunsontheGeneralizedFlightOperationsProcessingSimulator(GFLOPS) and is called the GFLOPS Rapid Real-time Development Environment (GRRDE). GRRDE provides publish-subscribe communication services between software components. These services help to reduce the complexity of managing software interfaces. The hard real-time performance of these services has been verified with General Timed Automata modelling demonstrating the usefulness of formal analysis techniques for flight software applications.

For educational purposes there is a need to teach electrical and computer engineering students the basics of the design of state machines using programmable logic devices, and for students interested in mobile robots to teach them the basics of mobile robots' behaviors. At the same time one of the topics of interest in the mobile robot's community is how to generate their new behaviors, using state machines, automatically. This paper discusses how to create mobile robots' behaviors using genetic algorithms (GAs), implementing them in programmable logic devices (FPGAs) and how these behaviors can be programmed by students in a mobile robotics course. The behaviors are encoded as algorithm state machines and using feed-forward artificial neural networks (ANN). In the state-machine approach, each individual's chromosome represents, given a set of inputs coming from the sensors and the current state, both the next state and the outputs that control the robot's movements. In the ANN approach, whose weights are found also with GAs, a pipeline architecture was built to perform it, each pipeline executes a layer of the ANN, thus once the pipeline is full the execution speed of the ANN is one sensors' clock cycle. We evaluate the behaviors generated by the GA according to a fitness function that grades their performance for avoiding obstacles. The inputs to such a robot are infrared sensors to detect obstacles, the outputs are the velocities of its wheels. Our objectives are first, to prove that GAs are a good option as a method for finding behaviors for mobile robots' navigation, and second, that these behaviors can be implemented in an efficient way in FPGAs. We tested both behaviors in a small mobile robot, that is build in an electrical engineering course that teaches how to build mobile robots.

A discrete event approach to micro-scale traffic modeling in urban environment

The High-rate Delay Tolerant Networking (HDTN) project at the NASA Glenn Research Center (GRC) is developing a performance-optimized Delay Tolerant Networking (DTN) implementation using the Bundle Protocol (BP) both for infusion in modern, distributed spacecraft systems and for foundational network research purposes. While one purpose of networking is to enable a returns-to-scale with communicating assets, it is recognized that neither the protocol nor its implementations may impose a bottleneck on data delivery if expected to be implemented. With this in mind, this paper explores the current status of the HDTN software, including its capabilities and also various performance metrics at the bundle layer, the convergence layers (e.g. performance-optimized Licklider Transmission Protocol, or LTP), and bundle storage and retrieval. This includes goals of software implementations that support multi-gigabit per second communications regardless of payload size. A discussion on the current software architecture and internal scheduling and routing is included. Interoperability with such extant DTN implementations as Interplanetary Overlay Network (ION) and DTN Marshall Enterprise Implementation (DTNME) are included. The research goals of the project are also listed, including Software-Defined Networking (SDN) and the theory of DTNs. A table-based filtration system for the Bundle Protocol (BP), called BP Filter, is also explored: this addition enables table-based policies within the context of a DTN for management purposes. Infusion begins with systems testing in the Johnson Space Center (JSC) Software Development and Integration Laboratory (SDIL), which supports International Space Station (ISS) Flight Software development, integration, and verification. Observations made from the results of testing in the SDIL and in flight testing are also discussed, pointing to a path for infusion into high data return low-earth orbit (LEO) missions. The paper concludes with areas for future work.

The aerospace industry is undergoing unprecedented transformation. New players, new ventures, and new technologies drive the established business towards a transition from traditional models and strategies to automated production and innovative methods. Software architecture for space systems needs to become more agile while preserving a high standard of quality. To that end, the rigorous verification and validation process that yields high quality software products should embrace automation and take full advantage of COTS hardware and software products. In line with the industry transformation, SSL’s Flight Software Development and Validation Department uses a modular, layered architecture that has evolved over decades of orbital experience. This paper describes the SSL Flight Software Development and Validation Workflow Management System and the advantages of such a system/framework for development and verification of very complex spacecraft. This system/framework allows faster cyclical test-fix-test process and also provides a platform that can be extended for a multitude of applications.

The CPU Utilization Statistics Plotter (CUSP) tool automates the interpretation of detailed CPU Utilization trace data and statistics. It puts you on the cusp of understanding how CPU resources are split among the many parallel components of a software system. CUSP combines time-sampled CPU utilization numbers and Event Log annotations to generate human-readable plots and tables. It automatically splits up large CPU usage log files around interesting events, determines and highlights just the tasks of primary relevance by evaluating their changing contribution to each plot's total CPU usage, automatically eliminates irrelevant tasks, provides context by labeling plots with names and durations of all active commands, and uses consistent color-coding to enable quick visual comparison across multiple plots. CUSP has been used to process CPU Utilization trace logs on the Mars Science Laboratory and the Mars 2020 Rover missions during flight software development and Flight Operations on the Martian surface since December 2013.

Discrete time software reliability modeling with periodic debugging schedule

Digital electronics is core curriculum in electronics and electrical engineering degrees. Programmable logic has now become its dominant implementation technology. We describe an integrated framework of practical work to support conventional (taught) design material, at all stages of an undergraduate degree course. Logic gate functions and state machines are first illustrated with demonstration units based on Programmable Logic Devices (PLDs). Students then use ABEL - a simple HDL (Hardware Description Language) - to implement a series of designs based around counters and state machines. A design exercise early in the second year requires students to use VHDL (VHSIC Hardware Description Language) to control a model lift with a simple FPGA (Field Programmable Gate Array), extending programmable implementation as well as programming language. Later work in the second year includes intensive team design projects involving programmable logic, and the design and test of a CMOS Gate Array system. All students therefore acquire transferable HDL skills. These can be developed further in the third year individual design project, where a range of HDL systems is available and it is easier to provide relatively expensive software for the limited numbers concerned. PLD programming is supported in two distinct ways. Conventional stand-alone programming stations provide for EPROMs and many PLDs, while in-system programming of standard architectures avoids bottlenecks in whole-class exercises. Hence, students are exposed to appropriate implementation technology in a manner suited to each level of their degree programme, to prime them well with transferable skills for their professional engineering careers.

An analogy between pure mathematics and the operational mathematics of Heaviside by means of the theory of H-functions

The microprogrammed approach to implementing control state machines has been used widely since the early 1960s and has the advantages of structured programming and fixed timing characteristics. With microprogramming, state machine changes require only a change in memory contents, so the rate at which the controller can be clocked does not change no matter how significant the program change. This approach is in contrast to the standard state machine approach with state transitions described in a hardware description language like VHDL or Verilog, where design changes can dramatically impact the logic equations, amount of combinational logic, and clock frequency. This article introduces the microprogramming technique and presents a microprogrammed control unit that has been tailored to implementation in field programable gut arrays. The sequencer presented supports both nested subroutines and nested loops and can operate in both pipelined and non‐pipelined modes. Althouse not attractive for a small number of states, the microprogrammed approach has significant advantages for complex controllers with a large number of states.