VO 2 Oscillator Circuits Optimized for Ultrafast, 100 MHz‐Range Operation

The design and simulation of a novel high-speed programmable counter circuit for 5GHz frequency synthesizer application in WLAN is presented. Compared with the conventional programmable counter circuit, it has a higher speed by using high-speed dual modulus prescaler (DMP) architecture that can operate as fast as asynchronous divider circuits and a new programmable counter structure. The proposed DMP circuit makes uses of the character of asynchronous circuits to increase running frequency. Based on this topology, a programmable counter is implemented in 0.18 μm TSMC standard CMOS process. Simulation result shows that a maximum operating frequency 6.3GHz is obtained at 1.8V supply voltage with a power consumption of 6.7 mW for the proposed DMP architecture and that a maximum operating frequency 4GHz is obtained at 1.8V supply voltage for the conventional DMP using the same synchronous part. Simulation result also shows that the proposed programmable counter can operate between 0.1GHz and 6.3GHz correctly.

This paper introduces the class-E power amplifier with only the MOSFET nonlinear drain-to-source parasitic capacitance as a shunt capacitance for the class-E sub-nominal condition, i.e., zero-voltage-switching (ZVS) condition at any grading coefficient m of the MOSFET body junction diode and any duty ratio D. The obtained analytical expressions for waveforms and design equations show that the grading coefficient m and the duty ratio D can be used as the adjustment parameters, which increases the degree of the design freedom by two. The switch-voltage waveform does not satisfy the class-E switching condition when the grading coefficient m is different from the design specifications, which resulted in the power conversion efficiency degradation. On the other hand, the duty ratio D is determines the location of the class-E switching conditions. Therefore, the grading coefficient m and the duty ratio D are important parameters to satisfy the class-E sub-nominal condition. Although, the maximum operating frequency and the output power capability are affected by the duty ratio D, only the maximum operating frequency is affected by the grading coefficient m. We obtained the analytical expressions, which are validated by PSpice simulations and laboratory experiments that the grading coefficient m is considered. The measurement and PSpice simulation results agreed with the analytical expressions quantitatively, which show the validity of our analytical expressions.

A transducer for placement in fixed relation to the axle/wheel assembly of a vehicle and adjacent to the body of the vehicle, the transducer cooperating with the vehicle body to form a reactance that has a magnitude proportional to the distance between the transducer and the vehicle body. The magnitude of the reactance thus varies in response to variations in distance between the vehicle body and the transducer when the body is caused to experience oscillation on the springs thereof. Such oscillation is damped by the vehicle shock absorbers. A capacitive transducer and an inductive transducer, both of which include a guard or shield which shields the transducer from ground. An oscillator circuit wherein the frequency of oscillation is determined by the above mentioned reactance, the oscillator circuit having a non-ground common to which the guard is connected. A method for testing shock absorbers by employment of the transducer and oscillator circuit which includes the steps of displacing the vehicle from a quiescent position to load the springs in the vehicle, releasing the vehicle body so that it can return to the quiescent position and measuring the time variation of the reactance as the vehicle body vibrationally returns to the quiescent condition so as to afford an objective evaluation of the damping action of the vehicle shock absorbers.

GaN HEMT devices exhibit improved performance in terms of switching speed and reduced on-state resistance, especially if low-voltage and high-frequency conditions are considered. In this paper, a high-power density quasi-resonant converter is proposed in order to improve both the maximum output power and the maximum operating frequency with GaN HEMT devices. Since the proposed converter operates as a class-E converter, there is no negative current flowing through the switching devices, perfectly matching the GaN HEMT devices restrictions. Besides, the proposed converter reduces the component count by using the parasitic output capacitance for high switching applications. An analytical model of the resonant converter operation is proposed in this paper, with special emphasis in the design equations, and an experimental prototype has been built to prove the feasibility of the proposed converter.

In this paper, an ultrafast high voltage pulse generator based on power MOSFETs delay push-pull structure is designed. The two complementary power MOSFETs are connected in the push-pull circuit and driven by the low-power MOSFETs separately. The output ultrafast high-voltage pulse amplitude is +30 V ~ -200 V, and the front edge and back edge times of the pulse are 5 ns and 4 ns, respectively. The width and frequency of the output pulse are controlled by the external trigger input signal. The shortest output pulse width is 12 ns and the maximum operating frequency is 100 kHz while the load is 10 pF. The delay conduction method of power MOSFETs is helpful to reduce power dissipation and improve the reliability of the circuit at a high operating frequency.

We report on the successful demonstration of a functionally complete set of logic gates based on resonant interband tunneling diodes (RITDs) with a maximum operating frequency in excess of 12 GHz. At this high frequency of operation, the power dissipation is remarkably low-on the order of 0.5 mW per gate. The circuits for all gates, AND, OR, XOR, and INV, shared the same layout geometry, consisting of two Schottky diodes and three RITDs. Logical functionality was determined solely by varying the relative areas of the devices.

Radiated emissions from simple digital circuits were found to depend both on the circuit layout and the choice of logic family. However, the difference in peak emissions between two logic families was found to be independent of circuit layout. The greatest difference in peak emissions was between high-speed 74 ACT logic and low-speed 4000 CMOS logic devices, with a mean value of approximately 20 dB. Emissions from a more complex circuit were compared with the measurements on simple loop circuits. For each logic family, test circuits were used to measure the rise and fall times, the maximum operating frequency and the transient switching currents between two successive logic gates. Empirical formulae have been derived which relate relative peak emissions to these switching parameters. These are more accurate than an analytical solution that assumes the switching waveform to be a perfect trapezoid.

Chapter 15 - Sine Wave Oscillators

In this paper we present several monolithically integrated push-push oscillators in the frequency range from 47 GHz to 190 GHz. The MMICs are fabricated in a production near SiGe:C bipolar technology developed by Infineon Technologies AG. The transistors show a maximum transit frequency of f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> =200 GHz and a maximum frequency of oscillation f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> =275 GHz. The passive circuitry is realized using integrated transmission-line components, integrated spiral inductors, MIM-capacitors and TaN resistors. The frequency of the output signal of the oscillators can be tuned either by varying the bias voltage of the whole oscillator circuit or using the capacitance variation of a base collector junction as a tuning varactor. Some of the oscillators show excellent phase noise behavior, especially the 190 GHz oscillator gives a world record in output power and phase noise for HBT-oscillators

The maximum operating frequency of the class E amplifier with nonlinear shunt capacitance depends on the transistor duty ratio. It varies with the duty ratio under zero-voltage switching (ZVS) and zero-derivative switching (ZDS) conditions at fixed values of the output power, dc supply voltage. Therefore, the design of the class E amplifier with given values of the shunt capacitance, the output power, dc supply voltage is possible by adjusting the operating frequency. The operating frequency has the maximum value when the duty ratio D <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> is approximately 0.36 at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> /V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bi</inf> =1 . It is also shown that the maximum operating frequency is higher when the dc supply voltage V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> is lower.

300-GHz-band transceiver chipsets with 40-nm CMOS process has been realized. A 300-GHz-band transmitter generates a modulated signal with 105 Gbps at the maximum, and the receiver demodulates a modulated signal of a maximum of 32 Gbps. The most difficult point in designing a 300-GHz-band transceiver with CMOS process is that the maximum operating frequency (f max) of transistors does not reach 300 GHz. Key technologies for designing a transceiver circuit exceeding the maximum operating frequency of transistors and the measurement results will be described.

In this paper, a Nios II processor based hardware/software co-design architecture with high expandability and development flexibility is proposed. The architecture integrates a pipelined color space converter (CSC), hardware accelerator (HA), and a LCD touch module (LTM) HA, which facilitates a high-speed implementation of RGB to YCbCr color space conversion with a real-time image display. To avoid the inefficiency of CSC circuit architecture due to massive floating-point multiplication operations in the conversion formulae, a GA-based evolutionary technique is used to realize the fast multiplierless CSC hardware architecture. Meanwhile, a pipeline design method is further applied to enhance the maximum operating frequency in circuit design. As compared to the commonly used floating-point based CSC architecture, the pipelined CSC HA in this paper has excellent advantages of low-complexity and high speed. After the mechanism is integrated into a system-on-a-programmable-chip (SOPC), the maximum operating frequency reached 168.12 MHz. That is, in every 0.11 s, the color space conversion can process a 512 × 512 image. This excellent result is practical to the fast development of different kind of image/video processing systems.

We performed a comprehensive investigation of the relationship between the maximum operating frequency of the NbN superconducting frequency divider and the key parameters of the NbN Josephson junction (JJ). We designed a superconducting frequency divider that uses a single NbN JJ as a pulse generator, several NbN Josephson transmission lines, an NbN Toggle Flip-flop, and a load. By comparing the bias voltage V in of the pulse generator with the output voltage V out of the load, we determined if the circuit was working correctly and calculated the maximum operating frequency f max. Additionally, we employed JSICsim software for simulations to analyze the impact of key parameters of the NbN JJ, such as critical current density J c, gap voltage V g, characteristic voltage V c, quality factor Q, and specific capacitance C s, on f max. The simulation results demonstrate that f max increases with increasing J c and Q. Specifically when J c exceeds 300 kA cm−2 and Q surpasses 4, the superconducting frequency divider can achieve a f max of 1 THz. Furthermore, we successfully fabricated a superconducting frequency divider using a 10 kA cm−2 process and tested a f max of 260 GHz, with a deviation of approximately 6% from the simulation results.

Two methods for determining a realistic maximum operating frequency for TTL gates are developed. Both methods involve using propagation delay times and redefining them to valid TTL levels. The first method is a rigorous treatment of the subject, while the second is an easy-to-use rule of thumb. The exponential-linear method, which is extensively discussed, is slightly conservative. No devices tested during this study would have failed due to the maximum operating frequency (f/sub MAX/) computed using this technique. The linear-linear technique is less conservative; several devices in this study would have failed to meet f/sub MAX/ requirements had this technique been used. >

A high speed dual-phase dynamic-pseudo NMOS ((DP)/sup 2/) latch using clocked pseudo-NMOS inverters is presented. Compared to the conventional D-latch, this circuit has a higher maximum operating frequency and consumes lower dynamic power at a given operating frequency. The latch has been demonstrated by utilizing it in the synchronous counter section of a dual-phase dual-modulus prescaler implemented in a 0.8 /spl mu/m CMOS process. The maximum operating frequency for the prescaler at 3 V supply voltage is 1.3 GHz, while the power consumption is 9.7 mW. This power consumption is significantly lower than those of the previously reported prescalers implemented in 0.8 /spl mu/m CMOS processes. The 9.7 mW power consumption at 1.3 GHz also compares favorably to the 24 mW power consumption of the 1.75 GHz prescaler using MOS current mode latches implemented in a 0.7 /spl mu/m CMOS process. A 25% reduction of the maximum operating frequency for a /spl sim/60% reduction of the power consumption should be a useful tradeoff.