Vortex-based spin transfer oscillator compact model for IC design

Introduction. Recent studies into the properties of spintronic oscillators have led to broadening their scope of practical application as devices for generating and processing signals. The practical implementation of spintronic oscillators is, however, significantly limited by their low power capacity, thus requiring synchronization between devices.Aim. Determination of conditions for the implementation of the synchronous regime of two antiferromagnetic spintronic oscillators coupled by a common current.Materials and methods. To simplify the numerical simulation of a system of coupled resistively antiferromagnetic oscillators, the method of multiple-time-scale analysis was used. This allowed a system of Kuramoto equations to be considered instead of the original system. To determine the locking band of the Kuramoto model, the homoclinic trajectory approximation method was applied.Results. A system of Kuramoto equation for the phases of partial oscillators under the influence of the inertial term and phase shift was obtained. Expressions describing the locking and synchronization band as functions of the system parameters (bias currents and sizes) were derived. The numerically simulated Kuramoto model was used to determine the bands of the synchronous and asynchronous regimes.Conclusion. The results of numerical simulations of the system of Kuramoto equations and the Adler equation for two coupled spintronic oscillators agree well with the theoretically calculated values of locking and synchronization ranges. The scheme for reducing the model of antiferromagnetic oscillators to a Kuramoto model can be further extended to the case of a larger number of coupled oscillators, which will simplify computational experiments and significantly reduce the time required for numerical simulations.

Microelectromechanical (MEMS) resonators are widely used in time-keeping and sensor applications due to their high quality factors and good frequency stability. In these applications, the function of MEMS resonators are often realized by driving them into self-sustained oscillations to maintain continuous tracking of changes in frequency. However, the small size and mass also make these resonators extremely sensitive to thermal fluctuations and easily become nonlinear, both of which highly degrade their performance in precision measurements. In this thesis, I explore methods of phase noise reduction on MEMS resonators driven into self-sustained oscillations. I design a microelectromechanical trampoline resonator with its eigenfrequency obeying a non-monotonic relationship with energy. Near the extremum energy, where the eigenfrequency does not change, the resonator behaves almost like a linear resonator even if the vibration amplitude is large. The noise driven response spectra becomes narrower when the noise intensity is increased. When the resonator is driven into self-sustained oscillation by a phase locked loop, the phase noise at the extremum amplitude is ~3 times smaller than the minimum of the conventional nonlinear resonator. I also design a two-mode microelectromechanical system. A pump at the red secondary sideband of the high frequency mode induces strong nonmonotonic positive nonlinear friction on the low frequency mode which significantly changes the dynamics of the oscillator. I study the generic features of parametric driven responses of the oscillator under such nonlinear friction. I demonstrate the electrostatic tuning of bifurcation topology of the oscillator. I present the noise squeezing from the merging of five states. In addition, I observe direct cooling on a nonzero amplitude state in the parametric oscillator in simulation. The phase noise is reduced by a factor of 1.8 compared with ordinary parametric oscillator.

Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current on current signatures and its impact on the diagnosis of such defects. The authors demonstrate that the impact of downstream current is minimized at low power supply (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> ) values. Therefore, current measurements at low power supply voltages are proposed to enhance bridge diagnosis. Experimental evidence of this behaviour is presented for real devices. Furthermore, current signatures measured at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VLV</sub> are used for the diagnosis of fifteen failing 0.18mum technology devices, which are demonstrated to contain a bridging defect.

This paper presents a CMOS-based Chebyshev current-mode ladder band-pass filter (BPF). The integrator building blocks (lossy and lossless integrators) with 6 grounded capacitors are used to realize the BPF by using doubly terminated RLC ladder filter prototype based on TSMC 0.18μm CMOS technology. Frequency response of the circuit can be tuned between 1MHz and 200MHz through bias currents from 0.01 μA to 100 μA. The proposed circuit has many attractive features, for instant, low power supply as 1.5V, low dynamic power consumption and low Total Harmonic Distortion (THD). All simulation results are carried out by PSpice which are good agreements compared with the RLC prototype.

A brief review of the impact of Bias-Temperature Instability (BTI) on Integrated Circuits (IC) is presented. The importance of this problem with the performance degradation on commercial IC designs, such as Physical Unclonable Functions (PUF) and Ring Oscillator (RO), which are key elements on security applications, is emphasized. A physical interpretation of this phenomenon is provided along with a brief description of the model's evolution, commonly used to simulate the degradation of transistor's parameters at high temperature and voltage supply conditions. Finally, some reported techniques are described to accomplish a better IC design, from the Process, Temperature and Voltage (PVT) variations point of view, lifetime yield optimization and weak spot detection on circuit's architecture.

Semiconductor micro/nano‐cavities with high quality factor (Q) and small modal volume provide critical platforms for exploring strong light‐matter interactions and quantum optics, enabling further development of coherent and quantum photonic devices. Constrained by exciton binding energy and thermal fluctuation, only a handful of wide‐band semiconductors such as ZnO and GaN have stable excitons at room temperature. Metal halide perovskite with cubic lattice and well‐controlled exciton may provide solutions. In this work, high‐quality single‐crystalline cesium lead halide CsPbX3 (X = Cl, Br, I) whispering‐gallery‐mode (WGM) microcavities are synthesized by vapor‐phase van der Waals epitaxy method. The as‐grown perovskites show strong emission and stable exciton at room temperature over the whole visible spectra range. By varying the halide composition, multi‐color (400–700 nm).WGM excitonic lasing is achieved at room temperature with low threshold (~ 2.0 μJ cm−2) and high spectra coherence (~0.14–0.15 nm). The results advocate the promise of inorganic perovskites towards development of optoelectronic devices and strong light‐matter coupling in quantum optics.

A predictive MOSFET model is very critical for early circuit design in nanoscale CMOS technologies. In this work, we developed a new compact MOSFET model which can dramatically improve the predictability of BSIM4 for the major 3 process and 2 layout variations by applying the simple physics-based equations to model these parameters. The accuracy of the model is verified using numerical TCAD simulation results and measurements under full range of temperature and bias conditions. The compact model for the circuit simulation can be efficiently used to predict the effects of process and layout variations on the circuit characteristics.

Reduction of power dissipations in CMOS circuits needs to be addressed for portable battery devices. Selection of appropriate transistor library to minimise leakage current, implementation of low power design architectures, power management implementation, and the choice of chip packaging, all have impact on power dissipation and are important considerations in design and implementation of integrated circuits for low power applications. Energy-efficient architecture is highly desirable for battery operated systems, which operates in a wide variation of operating scenarios. Energy-efficient design aims to reconfigure its own architectures to scale down energy consumption depending upon the throughput and quality requirement. An energy efficient system should be able to decide its minimum power requirements by dynamically scaling its own operating frequency, supply voltage or the threshold voltage according to a variety of operating scenarios. The increasing product demand for application specific integrated circuit or processor for independent portable devices has influenced designers to implement dedicated processors with ultra low power requirements. One of these dedicated processors is a Fast Fourier Transform (FFT) processor, which is widely used in signal processing for numerous applications such as, wireless telecommunication and biomedical applications where the demand for extended battery life is extremely high. This paper presents the design and performance analysis of a low power shared memory FFT processor incorporating dynamic voltage scaling. Dynamic voltage scaling enables power supply scaling into various supply voltage levels. The concept behind the proposed solution is that if the speed of the main logic core can be adjusted according to input load or amount of processor's computation "just enough" to meet the requirement. The design was implemented using 0.12 &#956;m ST-Microelectronic 6-metal layer CMOS dual- process technology in Cadence Analogue Environment.

Organic electronics has drawn considerable attention of the researchers with organic thin film transistors (OTFTs) as key components for various applications. Compared to the silicon industry where public models are well defined and commonly used to provide designers with a relative good description of any process, organic devices are still lacking for their complete device models that can fully describe their electrical characteristics. Therefore, compact model development for OTFTs is very important for development of this emerging field of OTFTs and organic electronics. In this paper we present a simple and efficient compact model for organic thin film transistor (OTFT) which can describe DC I-V characteristics of N-channel OTFT as well as P-channel OTFT. Model has been implemented in Verilog-A and simulations have been performed using Smart Spice analog circuit simulator from Silvaco Inc. Keywords: Compact modeling, Organic Thin Film Transistors (OTFTs), Simulation Program with Integrated Circuit Emphasis (SPICE), SmartSpice, Verilog-A Cite this Article Narendra Singh Kushwah, Dwivedi ADD. Computer Modeling of Organic Thin Film Transistors (OTFTs) using Verilog-A. Journal of Microelectronics and Solid State Devices . 2018; 5(1): 1–7p.

Low temperature detectors have been a subject of intense interest to the scientific community over the last decade. These detectors work at very low temperatures, often well below 1 Kelvin, to minimize the noise in the measurement of photons. This leads to very powerful detectors applicable to a broad wavelength range. Since these detectors are so sensitive even single pixels and small arrays (up to several hundred pixels) enable deeper explorations of the cosmos than ever before. Instruments based on these technologies have been used at submillimeter, optical, and X-ray wavelengths. The scientific prospects for these detectors increase as they grow in pixel count. For some applications, especially for Cosmic Microwave Background (CMB) polarization work, a large focal plane will not only increase efficiency but will also enable new and vital science. Current superconducting technologies, such as Transition Edge Sensors (TESs), can currently deliver extremely high sensitivity in the submillimeter and read-noise free imaging spectroscopy at Optical/UV and X-ray wavelengths, but the largest arrays contain less that 100 pixels. In order to make real progress these arrays must contain many thousands of pixels. This is a formidable technical challenge. This thesis will explore a promising emerging technology called Microwave Kinetic Inductance Detectors (MKIDs). MKIDs make use of the change in the surface impedance of a superconductor as incoming photons break up Cooper pairs. This is accomplished by making the strip of superconductor part of a microwave resonant circuit, and monitoring the phase of a signal transmitted through (or past) the resonator. The primary advantage of this technology is that by using resonant circuits with high quality factors, passive frequency domain multiplexing will allow up to thousands of resonators to be read out through a single coaxial cable and a single HEMT amplifier. This eliminates the cryogenic electronics (SQUIDS) and wiring problems associated with current superconducting devices. Inexpensive and powerful room-temperature readout electronics can leverage the microwave integrated circuits developed for wireless communications. When this project started four years ago MKIDs were just a concept. In this thesis I will recount the progress we have made in taking this concept and turning it into a detector technology, building on the work we published in Nature in 2003. I will demonstrate that we have overcome the major technical obstacles and shown conclusively that MKIDs work, and should provide much larger arrays than are possible with other technologies. Due to our work at Caltech and JPL, MKIDs are considered one of the leading technologies to reach the ambitious goals set for future ground and space missions. The noise performance is already good enough for sky-limited, ground-based, submillimeter astronomy. Despite MKIDs acceptable noise performance for ground-based astronomy, there are many applications which require lower detector noise. The simple MKIDs we measure in this thesis still exhibit a noise higher than theory would predict which could limit their usefulness for some applications. In Chapters 7-9 we perform several experiments which identify the source of the excess noise as the substrate. In the course of these experiments to characterize and identify the noise, we successfully demonstrate two distinct approaches which dramatically reduce the noise excess.

One of the key mandates of modern optoelectronic research is the development of compact photonic integrated circuits, capable of performing many diverse functions for the generation, manipulation, and detection of light, all on a single chip. A key practical requirement for such circuits is the development of optical devices for the localization and processing of light within extremely small dimensions. In recent years, planar microring and microdisk resonators, in which light is confined by total internal reflection, have emerged as versatile photonic elements for filling this role. The high quality factors and long photon storage times associated with the whispering-gallery modes supported by these microcavities result in several technologically useful characteristics, including narrow-band filter response, and large resonant enhancement of the circulating electric field. These properties have been exploited in numerous passive and active device applications, including optical add/drop multiplexers, all-optical switches, and tunable lasers. This thesis describes the study of several unique ring-based optical microcavity geometries based upon the indium gallium arsenide phosphide/indium phosphide alloy semiconductor material system, undertaken in an effort to explore new optoelectronic architectures for confining and manipulating light. The first portion of this work involves the analysis and demonstration of a new microcavity geometry, in which cylindrical Bragg reflection is used for radial optical confinement, as an alternative to total internal reflection. In this class of structures, collectively known as annular Bragg resonators, light can be guided within a ring or pillar defect layer surrounded by cylindrical Bragg mirrors. Several microcavities based upon this configuration are designed and fabricated using a thin InGaAsP quantum well membrane. Using pulsed optical excitation, the characteristics of these structures as low threshold vertically emitting lasers is explored. Second, a total internal reflection-based coupled waveguide-resonator geometry, having applications to low power optical switching and modulation, is analyzed. This geometry makes use of the hybrid integration of a Mach-Zehnder interferometer with a racetrack resonator. Switching takes place using the Mach-Zehnder to control the coupling parameters in the vicinity of the critical coupling condition. Characterization of the static and dynamic output response of a thermooptically actuated InGaAsP-InP hybrid switch device demonstrates good ON-OFF switching contrast, microsecond response time, and reduced switching power in comparison with a conventional Mach-Zehnder configuration. Finally, this work concludes by examining both the annular Bragg resonator and hybrid switch geometries in application to chemical and biological sensing. Both microcavity devices are shown to possess unique characteristics making them ideal for sensitive monitoring of small changes in the refractive index of a chemical or biological analyte.

Timing jitter is an important factor in determining the limit of speed and scale of single-flux-quantum circuits. We estimated the timing jitter by a simple method using 2-bit shift registers. It was estimated by observing the transition between 1- and 2-mode operations while changing the bias current to the clock line. A sharp transition was observed in the shift register with a smaller number of Josephson junctions in the clock and data lines, suggesting the existence of a finite timing jitter. The timing jitter per Josephson junction was estimated to be 0.09 ps at a designed bias current. The temperature dependence supported that the timing jitter comes from thermal fluctuation.

Patch antennas are highly used in the last few years in domains like spaceships, satellites and missiles, cellular phones, radars, GSM, wide area computer networks and also wireless local areas. This is the result of their advantages, namely the small dimensions and weight, their low cost, ease of use, ease of integration in other circuits and capability to operate at 2 or 3 frequency values. Their disadvantages, among which low efficiency, high quality factor and a narrow bandwidth must be improved. In order to do so, we must previously study the influence of different parameters on their functioning. In this paper, three different feeding types will be implemented on patch antennas and the resulting parameters will be compared and analyzed. Also, different operating frequencies will be taken into account in order to determine the dimensions of such an antenna. Considering the Rogers RT Duroid 5880 dielectric and its standard thicknesses patch antennas will also be modeled and parameters like S parameters, the bandwidth, directivity, gain will be analyzed.

Emerging spin-torque nano oscillators (STNOs) and spin-Hall nano oscillators (SHNOs) are potential candidates for microwave applications. Recent advances in three-terminal magnetic tunnel junction (MTJ)-based SHNOs opened the possibility to develop more reliable and well-controlled oscillators, thanks to individual spin Hall-driven precession excitation and read-out paths. To develop hybrid systems by integrating three-terminal SHNOs and CMOS circuits, an electrical model able to capture the analog characteristics of three-terminal SHNOs is needed. This model needs to be compatible with current electric design automation (EDA) tools. This work presents a comprehensive macrospin-based model of three-terminal SHNOs able to describe the dc operating point, frequency modulation, phase noise, and output power. Moreover, the effect of voltage-controlled magnetic anisotropy (VCMA) is included. The model shows good agreement with experimental measurements and could be used in developing hybrid three-terminal SHNO/CMOS systems.

The design of the active RC integrator presented in this research utilizes a fully balanced technique and current-tunable frequencies to create the active RC integrator and reliable circuit. The circuit is made up of six npn bipolar junction transistors (BJT), six resistors (R), and a capacitor (C), with the fully balanced technique used to make the circuit structure uncomplicated and symmetrical with signal differencing. This approach results in a low number of internal devices in the circuit, making it an attractive option for integrated circuit (IC) development. One of the key features of the fully balanced current-tunable active RC integrator is its ability to be frequency-tunable with bias current (If). This feature enables the circuit to be used in a variety of applications, including filter circuits, communication signal generators, instrumentation signal generators, and various automatic controls. The fully balanced design also ensures that the circuit is stable and robust, even in the presence of device parameter variations. To evaluate the performance of the active RC integrator, simulations were conducted using Pspice.&#x0D; The results show that a fully current-tunable active RC integrator can be precisely tuned with the active bias to a value consistent with the theoretically calculated value. This demonstrates the efficiency and reliability of the circuit design and simulation method. The Monte Carlo (MC) method was also used to analyze the circuit performance in cases where the resistor (R) and capacitor (C) device had a 10 percent error and the transistor gain (β) was set to an error of 50 percent. The MC analysis showed that the phase shift (degree) and magnitude (dB) of the circuit were stable, and the circuit's performance was not significantly impacted by the device parameter variations. This further demonstrates the robustness and versatility of the fully balanced current-tunable active RC integrator design. Finally, harmonic distortion was evaluated to confirm the performance of the designed and developed fully balanced current-tunable active RC integrator. The results showed low levels of harmonic distortion, which indicates that the circuit is suitable for high-performance applications that require low distortion