3- https://doi.org/10.1049/el:20020047
Word-parallel CRC computation on VLIW DSP
- Jan 17, 2002
- Electronics Letters
- D Hubaux +1 more
Abstract
Cyclic redundancy check (CRC) is widely used for error detection. For optimal performances, a method has been developed for bit-parallel processing, but it may not take advantage of parallel processor architecture. Here, a method is proposed for using the full power of a very long instruction word (VLIW) digital signal processor (DSP) architecture in CRC computation. The method is at least four times faster for 8, 16 and 32 bits CRC.
- # Cyclic Redundancy Check
- # Cyclic Redundancy Check Computation
- # Very Long Instruction Word
- # Instruction Word
- # Digital Signal Processor
- # Digital Signal Processor Architecture
- # Processor Architecture
- # Signal Processor Architecture
- # Advantage Of Architecture
- # Parallel Architecture
