Work-In-Progress: Cyber-Physical Systems and Dynamic Partial Reconfiguration Scalability: opportunities and challenges

Application specific integrated circuits are used to provide real-time performance of handheld devices within the compact physical size and low energy dissipation. However, these circuits are inflexible for any modification like redesign and refabrication. Reconfigurable architectures are promising alternative for conventional computing devices such as application-specific integrated circuits. It provides high-level flexibility to adapt the applications through dynamic hardware customization even after fabrication. A reconfigurable computing system design considers the peculiarities of the targeted application domain along with architectural issues like dynamic reconfiguration, partial reconfiguration, hardware/software co-design and context management. A brief survey has been carried out to understand the concepts and applications of CGRA, FPGA, SoC, NoC, MPSoC, dynamic partial reconfiguration, hardware/software co-design, design-space exploration, multi-objective optimization, genetic algorithm and reconfigurable computing on wireless communications. This paper deals with the survey on modeling, design, implementation and evaluation of coarse-grained dynamically reconfigurable processor architectures targeting the real-time embedded computing domain.

This paper proposes an Energy Adaptive Feedforward Neural Network (EANN). It uses multiple approximation techniques in the hardware implementation of the neuron unit. The used techniques are precision scaling, approximate multiplier, computation skipping, neuron skipping, activation function approximation and truncated accumulation. The proposed EANN system applies the partial dynamic reconfiguration (PDR) feature supported by the FPGA platform to reconfigure the hardware elements of the neural network based on the energy budget. The PDR technique enables the EANN system to remain functioning when the available energy budget is reduced by factors of 46.2% to 79.8% of the total energy of the unapproximated neural network. Unlike the conventional operation that only uses certain amount of energy and cannot function properly if the energy budget falls below that energy level, the EANN system remains functioning for longer time after energy drop at the expense of less accuracy. The proposed EANN system is highly recommended in limited-energy applications as it adapts the hardware units to the degraded energy at the expense of some accuracy loss.

Embedded devices are equipped with specialized microcontrollers for each device. If an ultra-general purpose microcontroller with all peripherals existing, any kind of embedded device can be developed by such microcontroller. However, such microcontrollers cannot be built due to the scale and price. A dynamic partial reconfigurable microcontroller (DPR microcontroller), which has a function to switch circuits for each application, can realize an ultra-general purpose microcontroller that can be used for any application. For the realization and practical use of DPR microcontrollers, it is necessary to develop a hardware library-like structure in which optimized interface circuits for each peripheral device are designed in advance. In addition, the impact of dynamic switching of peripheral device interface circuits on performance has not been studied, so it is necessary to evaluate these effects. Using dynamic partial reconfiguration, we measure the execution time, circuit size of the entire system, and power performance improvement ratio of a single system that displays a binarized image on an LCD module after gray scaling and binarizing the image. The results show that the dynamic partial reconfiguration can be used to improve the performance of the system. As a result, we confirmed that the system works correctly even when dynamic partial reconfiguration is used. In addition, we were able to improve the processing speed by about 2.13 times compared with software processing, and reduce the circuit size by about 24%. We also achieved a 13.8-fold improvement in power consumption.

Dynamic Partial Reconfiguration (DPR) allows the targeted FieldProgrammable Array (FPGA) to selectively update portions of the programmable logic while the remainder of the fabric stays active. Previously, designers were required to manually create DPR systems with minimal support from Computer Aided Design (CAD) tools. Xilinx ® ’s PlanAhead TM software now automates much of the DPR system generation process for ISE-based DPR systems. This paper presents EuTOPIA (EDK TO PlanAhead Implementation Automation), a CAD tool that extends the automation in Xilinx’s current DPR design flow to include microprocessor based designs. Given an architecture described in Xilinx’s Embedded Design Kit (EDK), EuTOPIA automates the process of converting it into a PlanAhead project for a DPR design. EuTOPIA abstracts the low level details of DPR implementation so that designers need only have nominal knowledge of the underlying process to create their initial DPR system. EuTOPIA is shown to reduce implementation time by a factor of 18 times over manual implementations by experienced designers, and can be further increased for novice designers. Over the design-cycle of a product where designers may generate tens or even hundreds of different implementations of their DPR design, these time savings could be extremely significant.

Reconfiguration technique has been considered as one of the most promising electronic design automation (EDA) technologies in MPSoC design paradigms. However, due to the unavoidable latency in the reconfiguration procedure, it still poses a significant challenge to efficiently analyze the trade-offs for the software/hardware execution, static reconfiguration and dynamic reconfiguration. In this paper we first present a heterogeneous MPSoC middleware to support state-of-the-art dynamic partial reconfigurable technologies. Furthermore, we evaluate the reconfiguration latency and analyze the trade-off for the dynamic partial reconfiguration technologies.

A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of which at any given time only one needs to be realised. Using dynamic partial reconfiguration of an FPGA, all the modes can be implemented on the same reconfigurable region, requiring only an area that can contain the biggest mode. This can save considerable chip area. Conventional dynamic partial reconfiguration techniques generate a configuration for every mode separately. As a result, to switch between modes the complete reconfigurable region is rewritten, which often leads to long reconfiguration times. In this paper we give an overview of research we conducted to reduce this overhead of dynamic partial reconfiguration for multi-mode circuits. In this research we explored several joint optimization strategies at different stages of the tool flow.

Dynamic Partial Reconfiguration (DPR) is a promising technology ready for use, enabling the design of more flexible and efficient systems. However, existing design flows for DPR are either low-level and complex or lack support for automatic synthesis. In this paper, we present a SystemC based modelling and synthesis flow using the OSSS+R framework for reconfigurable systems. Our approach addresses reconfiguration already on application level enabling early exploration and analysis of the effects of DPR. Moreover it also allows quick implementation of such systems using our automatic synthesis flow. We demonstrate our approach using an educational example.

This paper presents a novel cell architecture for evolvable systolic arrays. HexCell is a tile-able processing element with a hexagonal shape that can be implemented and dynamically reconfigured on field-programmable gate arrays (FPGAs). The cell contains a functional unit, three input ports, and three output ports. It supports two concurrent configuration schemes: dynamic partial reconfiguration (DPR), where the functional unit is partially reconfigured at run time, and virtual reconfiguration circuit (VRC), where the cell output port bypasses one of the input data or selects the functional unit output. Hence, HexCell combines the merits of DPR and VRC including resource-awareness, reconfiguration speed and routing flexibility. In addition, the cell structure supports pipelining and data synchronization for achieving high throughput for data-intensive applications like image processing. A HexCell is represented by a binary string (chromosome) that encodes the cell's function and the output selections. Our developed evolvable HexCell array supports more inputs and outputs, a variety of possible datapaths, and has faster reconfiguration, compared to the state-of-the-art systolic array while maintaining the same resource utilization. Moreover, by using the same genetic algorithm on the two systolic arrays, results show that the HexCell array has higher throughput and can evolve faster than state-of-the-art array.

Recent research has shown that field programmable gate arrays (FPGAs) have a large potential for accelerating demanding applications, such as high performance digital signal process applications with low-volume market. The loss of generality in the architecture is one disadvantage of using FPGAs, however, the reconfigurability of FPGAs allow reprogramming for other applications. Therefore, a uniform FPGA-based architecture, an efficient programming model, and a simple mapping method are paramount for the wide acceptance of FPGA technology. This paper presents MASALA, a dynamically reconfigurable FPGA-based accelerator for parallel programs written in thread-intensive and explicit memory management (TEMM) programming models. Our system uses a TEMM programming model to parallelize demanding applications, including application decomposition into separate thread blocks and compute and data load/store decoupling. Hardware engines are included into MASALA using partial dynamic reconfiguration modules, each of which encapsulates a thread process engine that implements the hardware's thread functionality. A data dispatching scheme is also included in MASALA to enable the explicit communication of multiple memory hierarchies such as interhardware engines, host processors, and hardware engines. Finally, this paper illustrates a multi-FPGA prototype system of the presented architecture: MASALA-SX. A large synthetic aperture radar image formatting experiment shows that MASALA's architecture facilitates the construction of a TEMM program accelerator by providing greater performance and less power consumption than current CPU platforms, without sacrificing programmability, flexibility, and scalability.

FPGAs achieve smaller geometries and their reliability is becoming a severe issue. Non-functional properties, as Negative Bias Temperature Instability, affect the device functionality. In this work a novel methodology to address this issue is described, exploiting FPGAs flexibility. Dynamic Partial Reconfiguration is used to minimize aging impact on FPGAs' configuration memory.

Reconfigurable architectures become popular in consumer applications as they require low Non-Recurring Engineering costs. Certain FPGA families provide the Dynamic Partial Reconfiguration (DPR) mechanism which allows to modify parts of a device on-the-fly. The high reliability constraints in automotive systems requires safe communications between ECUs (Electronic Control Unit). This paper presents a support for fault-tolerant communication modes among ECUs by the use of the dynamic reconfiguration paradigm. Also in this paper, a method of integrating dynamic reconfiguration in Autosar environment is presented.

Field Programmable Gate Array (FPGA) architectures, such as Xilinx's Virtex-4 up to 7 series, have enabled partial and dynamic run-time self-reconfiguration for a long time. This feature enables the substitution of parts of a hardware design implemented on this re-configurable hardware, and therefore makes it possible for a system to adapt to the actual demands of applications. Dynamic Partial Reconfiguration (DPR) is an interesting technique that permits to share a part of the FPGA between different dedicated functions or hardware accelerators. Many domains may benefit from this technique including the Internet of Things (IoT), automotive industry, etc. However, many parameters, such as reconfiguration overhead, idle power consumption and performance trade-off, must be considered. In this paper, we provide a precise estimation of the power consumption when the DPR process is running in order to evaluate its influence on the performance of the global design. For this purpose, a Software/Hardware (SW/HW) system was implemented and the results were extracted in real-time using Zynq System on Chip SoC devices.

Debugging of Field-Programmable Gate Arrays (FPGAs) is a difficult task due to the limited access to the internal signals of the design. Embedded logic analyzers enhance the signal observability for FPGAs. These analyzers are implemented on the FPGA resources and they use the embedded memory blocks as trace buffers, so a limited number of signals can be observed using these analyzers due to resources constraints. Changing the traced set of signals requires re-synthesis, placement and routing of the whole design. In this paper, we propose a new methodology for FPGA debugging to change dynamically the set of signals to be observed at runtime, and consequently minimize the time required for debugging. The proposed methodology utilizes the Dynamic Partial Reconfiguration (DPR) technique to dynamically switch between different sets of signals. DPR creates a reconfigurable module (RM) to route each set of signals to an embedded logic analyzer. We demonstrate the proposed approach using Xilinx FPGA tools, finding that changing the set of signals to be observed requires only few milli-seconds to re-program the reconfigurable region (RR). The area overhead of the proposed methodology is lower than other traditional methods of using multiplexers as the DPR allows the routing module to only use buffers to connect a set of signals to the embedded logic analyzer.

Dynamic Partial Reconfiguration (DPR) of Xilinx FPGAs in cases where there is significant logic difference between subsequent configurations is made possible by Xilinx module-based PR flow. Xilinx supports this flow only for high-end FPGAs and requires paid license, without which Xilinx PlanAhead software disables the related knobs and features. This poster presents a unique methodology (called DPR-LD) that enables DPR of low-end and high-end Xilinx FPGAs and requires no paid license. DPR-LD stands for DPR for Large Differences. DPR-LD uses the free Xilinx difference-based bit file generation software (bitgen), which normally is meant only for small differences between subsequent configurations. DPR-LD can be realized through either FPGA Editor or PlanAhead. Our FPGA Editor flow requires several physical constraints to ensure contention-free implementation of static and dynamic modules. We use implementation, floorplanning, and placement constraints to partition the design into several physical regions (one per module) for mapping, packing, placement, and routing. In order to avoid routing of a module to cross over another module, are used to isolate the modules from each other. However, fortress blocks lead to wasted FPGA resources. On the other hand, in our PlanAhead flow, the physical constraints are entered via a GUI, and the corresponding actual physical constraints are generated automatically and without wasting FPGA resources. To evaluate the two approaches, a proof-of-concept application with a single dynamic region was implemented using both flows. In addition, a multiple dynamic region design was implemented with our PlanAhead flow.

Image filtering is a process in which noise is reduced from the tainted which is a vital task in image processing. In the recent years evolutionary design of image filters which provides hardware and adaptive implement able solutions has received a lot of attention. This work deals with the design of evolvable hardware (EHW), where it is a new field that brings mutually reconfigurable hardware, artificial intelligence, fault tolerance and autonomous systems. The evolvable hardware is special because of its adaptable architecture which changes according to the environment requirements. The EHW should include evolutionary techniques to attain the behavior of adaptableness. This architecture can evolve autonomously straight on the reconfigurable fabric of FPGAs, using Dynamic partial reconfiguration. This DPR gives very high flexibility to recognize the adaptive hardware algorithms.