Writing on Dirty Memory

In order to realize the high-performance solid-state drives (SSDs), SCM/NAND flash hybrid SSD has been proposed, which add Storage Class Memory (SCM) as a non-volatile cache to the NAND flash based SSD. This paper provides cache operation guidelines and the optimal SCM specifications for the hybrid SSD. Two algorithms, the hybrid SSD with 1) read-write cache and 2) write cache are discussed. SCMs are classified into two categories; memory-type SCM (M-SCM) and storage-type SCM (S-SCM). M-SCM is appropriate for hybrid SSD with write cache, while S-SCM is optimal for hybrid SSD with read-write cache. The impact of SCM read/write latency on the overall SSD performance is also analyzed. The required read/write latency of M-SCM and S-SCM are 0.1us/1us and 1us/3us, respectively to achieve 7-times higher performance compared with NAND flash based SSD. This means 10-times faster but one fourth smaller capacity M-SCM with write cache achieves the similar performance compared to S-SCM with read-write cache.

A great deal of research has been done on solid-state storage media such as flash memory and non-volatile memory in the past few years. While NAND-type flash memory is now considered a top alternative to magnetic disk drives, different types of non-volatile memory have also begun to appear in the market recently. Although some advocates of storage class memory (SCM) predicted that flash memory would give way to SCM in the very near future, we believe that they will co-exist, complementing each other, for a while until the hurdles in its manufacturing process are lifted and storage class memory becomes commercially competitive in both capacity and price. This demo presents an improved design of In-Page Logging (IPL) by augmenting it with Phase Change RAM (PCRAM) in its log area. IPL is a buffer and storage management strategy that has been proposed for flash memory database systems. Due to the byte-addressability of PCRAM and its faster speed for small reads and writes, the IPL scheme with PCRAM can improve the performance of flash memory database systems even further by storing frequent log records in PCRAM instead of flash memory. We report a few advantages of this new design that will make IPL more suitable for flash memory database systems.

Solid-state drive (SSD) with flash memory as the storage medium are being widely used in various data storage systems. SSD data compression means that data is compressed before it is written to Not-And (NAND) Flash. Data compression can reduce the amount of data written in NAND Flash and improve the performance and reliability of SSDs. At present, the main problem facing data compression of SSD is how to improve the efficiency of data compression and decompression. In order to improve the performance of data compression and decompression, this study proposes a method of SSD data deduplication based on zone division. First, this study divides the storage space of the SSD into zones and divides them into one hot zone and multiple cold zones according to the different erasing frequency. Second, the data in each zone is divided into hot data and cold data according to the number of erasures. At the same time, the address mapping table in the hot zone is loaded into the cache. Finally, when there is a write or read request, the SSD will selectively compress or decompress the data according to the type of different zones. Through simulation tests, the correctness and effectiveness of this study are verified. The research results show that the data compression rate of this research result can reach 70–95%. Compared with SSD without data compression, write amplification is reduced by 5 to 30%, and write latency is reduced by 5 to 25%. The research results have certain reference value for improving the performance and reliability of SSD.

A hybrid of storage class memory (SCM) and NAND flash is a promising technology for high performance storage. Error correction is inevitable on SCM and NAND flash because their bit error rate (BER) increases with write/erase (W/E) cycles, data retention, and program/read disturb. In addition, scaling and multi-level cell technologies increase BER. However, error-correcting code (ECC) degrades storage performance because of extra memory reading and encoding/decoding time. Therefore, applicable ECC strength of SCM and NAND flash is evaluated independently by fixing ECC strength of one memory in the hybrid storage. As a result, weak BCH ECC with small correctable bit is recommended for the hybrid storage with large SCM capacity because SCM is accessed frequently. In contrast, strong and long-latency LDPC ECC can be applied to NAND flash in the hybrid storage with large SCM capacity because large-capacity SCM improves the storage performance.

The pursuit of non-volatile memory with program speeds below one nanosecond, beyond the capabilities of non-volatile flash and high-speed volatile static random-access memory, remains a longstanding challenge in the field of memory technology1. Utilizing fundamental physics innovation enabled by advanced materials, series of emerging memories2, 3, 4–5 are being developed to overcome the speed bottleneck of non-volatile memory. As the most extensively applied non-volatile memory, the speed of flash is limited by the low efficiency of the electric-field-assisted program, with reported speeds6, 7, 8, 9–10 much slower than sub-one nanosecond. Here we report a two-dimensional Dirac graphene-channel flash memory based on a two-dimensional-enhanced hot-carrier-injection mechanism, supporting both electron and hole injection. The Dirac channel flash shows a program speed of 400 picoseconds, non-volatile storage and robust endurance over 5.5 × 106 cycles. Our results confirm that the thin-body channel can optimize the horizontal electric-field (Ey) distribution, and the improved Ey-assisted program efficiency increases the injection current to 60.4 pA μm−1 at |VDS| = 3.7 V. We also find that the two-dimensional semiconductor tungsten diselenide has two-dimensional-enhanced hot-hole injection, but with different injection behaviour. This work demonstrates that the speed of non-volatile flash memory can exceed that of the fastest volatile static random-access memory with the same channel length.

Study of storage class memory (SCM) /NAND flash memory hybrid solid-state drive (SSD) is developed for enterprise storage system. The hybrid SSDs for enterprise applications require a large capacity. However, the larger hybrid SSD capacity becomes, the more energy is consumed. Then, through silicon-via (TSV) technology realizes to reduce energy consumption and footprint of the hybrid SSDs. In this paper, the energy consumption of three-dimensional (3-D) hybrid SSDs with the TSV are evaluated, and design guideline for the hybrid SSD system with the TSV is presented for application characteristics. From the evaluation results, the TSV is effective for the small-capacity low-end mobile hybrid SSD with the read-hot application, and 25.7% energy consumption reduction is obtained with the TSV. Additionally, the TSV is effective for the large-capacity high-end enterprise hybrid SSD with the read-cold application, and the energy consumption reduces by 56.6% with applying the TSV.

This study proposes a heterogeneous integration of precise and approximate storage in data center storage. The storage control engine allocates precise and error-tolerant applications to precise and approximate storage, respectively. The appropriate use of both precise and approximate storage is examined by applying a non-volatile memory capacity algorithm. To respond to the changes in application over time, the non-volatile memory capacity algorithm changes capacity of storage class memories (SCMs), namely the memory-type SCM (M-SCM) and storage-type SCM (S-SCM), in non-volatile memory resource. A three-dimensional triple-level cell (TLC) NAND flash is used as a large capacity memory. The results indicate that precise storage exhibits a high performance when the maximum storage cost is high. By contrast, with a low maximum storage cost, approximate storage exhibits high performance using a low bit cost approximate multiple-level cell (MLC) S-SCM.

Highly reliable solid-state drives (SSDs) with triple-level-cell (TLC) NAND flash and Advanced Error-Prediction Low-Density Parity-Check (AEP-LDPC) are proposed. To increase NAND flash's capacity, bits/cell have been doubled and tripled, which causes reliability to drastically degrade due to narrower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> margins. Previously proposed Error-Prediction LDPC (EP-LDPC) error-correcting code (ECC) improved reliability for Multi-Level-Cell (MLC) NAND flash [4]. However, in EP-LDPC program disturb is not modeled, so precision is limited, especially in short data retention <; 2 days. Here, AEP-LDPC is proposed for TLC NAND flash. By considering effects of program disturb, data retention and floating-gate capacitive coupling, the most accurate SSDs can be realized, with high speed read capability. The SSD's data-retention time increases by more than 12 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sup> , decode iterations decrease 57% and acceptable TLC NAND BER increases by more than 2.8 ×.

NAND Flash-based solid-state drives (SSDs) have been adopted in enterprise storage applications that require high capacity and high-throughput performance. In recent years, a SATA interface supporting only up to 600MB/S throughput has hindered the accelerating performance growth of SSDs due to the host bandwidth limit. A PCI Express (PCIe) has emerged to close the limit because it can deliver 1GB/s throughput per lane and can be scaled to multi-lane to improve bandwidth [1]. Accordingly, the SSD performance bottleneck has moved from the host interface to the NAND flash interface. In a memory system, a die-stacking technology in a NAND flash multi-chip package (MCP) effectively increases capacity and throughput performance in terms of PCB complexities and power consumption compared to a method increasing the number of channels. However, the multi-drop bus topology on NAND interfaces severely affects I/O speed degradations due to channel reflections and inter-symbol interference (ISI) resulting from large capacitive loadings [2]. The undeniable paradox between larger storage capacity and higher I/O bandwidth has become a key challenge to reach enterprise-class SSDs. To overcome this issue, this paper presents a frequency-boosting interface chip (F-Chip) to boost I/O speeds while meeting capacity requirements. A 2Tb NAND flash MCP with 1GB/s toggle DDR interface is accomplished by incorporating the F-Chip into the NAND MCP including a 16-die stacked 128Gb NAND flash [3].

Flash memory has become the storage medium of choice in portable consumer electronic applications, and high performance solid state drives (SSDs) are also being introduced into mobile computing, enterprise storage, data warehousing, and data-intensive computing systems. On the other hand, flash memory technologies present major challenges in the areas of device reliability, endurance, and energy efficiency. In this work, the error behavior of TLC flash is studied through an empirical database of errors which were induced by write, read, and erase operations. Based on this database, error characterization at the block and page level is given. To address the observed error behavior, a new error-correcting scheme for TLC flash is given and is compared with BCH and LDPC codes.

The integration limit of flash memories is approaching, and many new types of memory to replace conventional flash memories have been proposed. Unlike flash memories, new nonvolatile memories do not require storage of electric charges. The possibility of phase-change random-access memories (PCRAMs) or resistive-change RAMs (ReRAMs) replacing ultrahigh-density NAND flash memories has been investigated; however, many issues remain to be overcome, making the replacement difficult. Nonetheless, ferroelectric RAMs (FeRAMs) and magnetoresistive RAMs (MRAMs) are gradually penetrating into fields where the shortcomings of flash memories, such as high operating voltage, slow rewriting speed, and limited number of rewrites, make their use inconvenient. For instance, FeRAMs are widely used in ICs that require low power consumption such as smart cards and wireless tags. MRAMs are used in many kinds of controllers in industrial equipment that require high speed and unlimited rewrite operations. For successful application of new non-volatile semiconductor memories, such memories must be practically utilized in new fields in which flash memories are not applicable, and their technologies must be further developed.

In this paper, we proposed web performance enhancement of the e-business system using the SSD (Solid State Drive). In the e-business system, transactions must be strictly ordered, should occur at a fixed point time, and not be lost. We approached to solve e-business problem by using software and hardware techniques such as SSD. X-internet has advantage of C/S and Web applications. Since X-internet technique enables to reduce the loading time of web pages, X-internet is useful to enhance performance of the e-business system. SSD is a storage device that uses DRAM or NAND Flash as primary storage media. Since the SSD stores and accesses data directly to memory chips, which results in storage speeds far greater than conventional magnetic storage devices (HDD). Therefore x-internet techniques can be used to solve confused browsing and poor UI, and SSD can be used to solve I/O bottleneck of the e-business system.

Securely erasing data is of key importance to anyone that is concerned with the security of their sensitive information, whether an individual or an organization. Simply deleting the data in question or formatting the storage device is not enough to ensure that the data cannot be recovered. Furthermore, with the uptake of Universal Serial Bus drives (USBs) flash memory based storage devices have replaced previous portable secondary storage media. Therefore, it is of a major concern whether these tools and products developed for securely erasing data secondary storage Hard Disk Drives (HDDs) would be as efficient when targeting the USB flash memory storage devices. With a wide range of open source and commercial products available on the market, all claiming, among other things, to be able to securely delete your data, it is quite a difficult task for the consumer to pick the most efficient product. This paper therefore discusses the results of experiments conducted with both the open source and commercial tools which claim to securely delete data off USB flash memory storage devices.

This paper explores the topic of Solid-State Drives (SSDs) and NAND flash memory. Information of this paper is mainly obtained from authoritative academic websites and papers related to SSDs and flash memory. Memory cells are fundamental components in various electronic devices. In the field of data storage, SSDs represent the latest generation of storage devices, offering significantly better performance and functionality than traditional hard disk drives (HDDs). NAND flash memory chips are crucial component of SSDs, particularly 3D NAND, which exhibits exceptional performance and holds significant potential for future advancements. This paper will commence by providing an overview of SSDs and HDDs, followed by a comparison between NAND flash and NOR flash, and ultimately analysing the future of NAND flash memory technology employed in SSDs, with a focus on elucidating the advantages of 2D NAND over 3D NAND. Additionally, this paper explains a few challenges that NAND technology faces currently, as well as some possible solutions.

Solid state drives (SSD) are usually built using a NAND flash memory array. An SSD controller manages datastreams stripped to multiple flash memory channels. The device could be regarded as a level-0 structure of redundant array of independent disk (RAID), the technical term for a disk array system. This typical SSD controller architecture is called an intrinsic RAID (iRAID). An iRAID-based SSD controller has to execute sophisticated wear-leveling algorithms and dynamically calculate the lifespan of each flash memory chip as well as run error correction coding. redundant array of independent module (RAIM) was proposed to simplify the SSD controller by applying a group of standardized memory modules instead of raw flash memory chips. One of the widely recognized memory modules is the embedded multi-media card (eMMC) module, which is a small component, typically with a ball grid array package, and is found in consumer applications. In the paper, we have described the methods needed to optimize wear-leveling in an array of eMMC modules and deduced a formula to evaluate and optimize the lifespan of an RAIM-based SSD. A silicon SSD controller was implemented to verify the analysis. The positive result revealed that the lifespan of the RAIM-based SSD could be improved in consumer-grade eMMC modules.