XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks

This work proposes a 10T SRAM-based in-memory computation (IMC) architecture that can be configured to perform linear multiply-and-accumulate (MAC) operations and high-throughput XNOR-and-accumulate (XAC) operations. The IMC-MAC operation is performed by using the proposed scaled-voltage-based pulse count modulation (PCM) technique, which improves the linearity and signal margin of the MAC operation. The IMC-XAC operation is performed by using the proposed single capacitor discharge (SCD) approach with various advantages such as no deterministic error in XAC output, low latency, and less variation compared to the traditional charge sharing (TCS)-based XAC operation. The post-layout simulations of the proposed IMC architecture in a 65-nm CMOS process shows that the IMC architecture achieves a signal margin of 44.3 mV using the proposed scaled-voltage-based PCM approach in IMC-MAC mode whereas 37% less variation using the proposed SCD approach in IMC-XAC mode. In IMC-MAC mode, we achieve a 54.6 GOPS, 273 TOPS/W, and 98.67%/88.72% classification accuracy on MNIST/CIFAR-10 dataset using the convolution neural network (CNN)/ResNet20 algorithm. In IMC-XAC mode, we achieve a 3276.8 GOPS, 1092.2 TOPS/W, and 97.12% classification accuracy on the MNIST dataset using the binary neural network (BNN) algorithm.

We trained a binarized neural network (BNN) which can be used for handwritten digit recognition on software, and implemented this BNN on the FPGA using software training parameters without the help of high-level synthesis (HLS). This BNN contains an input layer, two convolutional layers, two pooling layers, a fully connected layer and an output layer. The first convolution layer contains 10 convolution kernels, each of which has a size of $5^{ \ast} 5$ . Each convolution kernel uses 25 arithmetic units to calculate in parallel, the calculation of 10 convolution kernels is also parallel. The size of the convolution kernels in the second convolutional layer is $3^{ \ast} 3$ , the input and output channels are 10, we use 900 XNOR gates for calculation here. Compared with the traditional CNN, it does not need to consume DSP resources and requires less storage space for the parameters. And the power consumption obtained by Quartus ii software of this BNN is 0.136 W. The time to identify a picture is $18 \mu \mathrm{s}$ , and the accuracy rate is 85% without the batch normalize (BN) layer.

Speaker verification based on deep neural network is one of the most prospective biometric authentication methods. But massive computation and parameters make it difficult to deploy speaker verification systems on memory and power constrained embedded devices. Binary neural networks with weights and activations compressed to 1 bit can reduce computational and memory cost significantly. However, speaker verification system based on binary neural networks suffers performance degradation problem. In this paper, to mitigate this problem and facilitate information flow across layers, we optimize binary neural network structure by adding a shortcut to connect layers. We propose an energy and memory efficient speaker system based on the optimized binary networks. Experimental results on text-dependent and text-independent datasets show that performance of proposed speaker verification system outperforms conventional binary neural networks significantly. Compared with full precision networks, the proposed system can largely maintain the performance while reducing memory and computational costs.

Binary Neural Networks (BNNs) show promising progress in reducing computational and memory costs, but suffer from substantial accuracy degradation compared to their real-valued counterparts on large-scale datasets, e.g., ImageNet. In this work we study existing BNN architectures and revisit the commonly used technique to include scaling factors. We suggest several architectural design principles for BNNs, based on our studies on architectures. Guided by our principles we develop a novel BNN architecture BinaryDenseNet, which is the first architecture specifically created for BNNs to the best of our knowledge. In our experiments, BinaryDenseNet achieves 18.6% and 7.6% relative improvement over the well-known XNOR-Network and the current state-of-the-art Bi-Real Net in terms of top-1 accuracy on ImageNet, respectively. Further, we show the competitiveness of our BinaryDenseNet regarding memory requirements and computational complexity.

A mixed-signal binarized neural network (BNN) processor for the MNIST image classification is demonstrated based on analogue circuit networks. BNN algorithm for training neural networks with binary weights and activations reduces power consumption and memory size. This algorithm is a design to perform core operations of multi-layer perceptron (MLP) to reduce complexity and power consumption using analogue circuits. The mixed-signal BNN processor employs a current mirror neuron to perform multiply-and-accumulate (MAC) operations and sign activation functions. The near-threshold current mirror neuron that computes the key operations of the BNN algorithm is used to achieve low power consumption. The design occupies 0.065 mm2 in 28-nm CMOS with 560B of on-chip SRAM. The 28-nm CMOS test-chip achieves energy efficiency of 24.1 TOPS/W and 94% accuracy on the MNIST image classification. This design with binary weights and activations exhibits only 5% degradation in accuracy compared with the models with floating-point precision.

Binary neural networks have recently begun to be used as a highly energy- and computation-efficient image processing technique for computer vision tasks. This paper proposes a novel extension of existing binary neural network technology based on the use of a Hadamard transform in the input layer of a binary neural network. Previous state-of-the-art binary neural networks require floating-point arithmetic at several parts of the neural network model computation in order to maintain a sufficient level of accuracy. The Hadamard transform is similar to a Discrete Cosine Transform (used in the popular JPEG image compression method) except that it does not include expensive multiplication operations. In this paper, it is shown that the Hadamard transform can be used to replace the most expensive floating-point arithmetic portion of a binary neural network. In order to test the efficacy of this proposed method, three types of experiments were conducted: application of the proposed method to several state-of-the-art neural network models, verification of its effectiveness in a large image dataset (ImageNet), and experiments to verify the effectiveness of the Hadamard transform by comparing the performance of binary neural networks with and without the Hadamard transform. The results show that the Hadamard transform can be used to implement a highly energy-efficient binary neural network with only a miniscule loss of accuracy.

Resistive random access memory (ReRAM) has been proven capable to efficiently perform in-situ matrix-vector computations in convolutional neural network (CNN) processing. The computations are often conducted on multi-level cell (MLC) that have limited precision and hence, show significant vulnerability to noises. The binarized neural network (BNN) is a hardware-friendly model that can dramatically reduce the computation and storage overheads. However, XNOR, which is the key operation in BNNs, cannot be directly computed in-situ in ReRAM because of its nonlinear behavior. To enable real in-situ processing of BNNs in ReRAM, we modified the BNN algorithm to enable direct computation of XNOR, POPCOUNT and POOL based on ReRAM cells. We also proposed the complementary resistive cell (CRC) design to efficiently conduct XNOR operations and optimized the pipeline design with decoupled buffer and computation stages. Our results show our scheme, namely, ReBNN, improves the system performance by $$25.36\times$$ and the energy efficiency by $$4.26\times$$ compared to conventional ReRAM based accelerator, and ensures a throughput higher than state-of-the-art BNN accelerators. The correctness of the modified algorithm is also validated.

The binarized neural network (BNN) is one of the most promising candidates for low-cost convolutional neural networks (CNNs). This is because of its significant reduction in memory and computational costs, and reasonable classification accuracy. Content-addressable memory (CAM) can perform binarized convolution operations efficiently since the bitwise comparison in CAM matches well with the binarized multiply operation in a BNN. However, a significant design issue in CAM-based BNN accelerators is that the operational reliability is severely degraded by process variations during match-line (ML) sensing operations. In this paper, we proposed a novel ML sensing scheme to reduce the hardware error probability. Most errors occur when the difference between the number of matches in the evaluation ML and the reference ML is small; thus, the proposed hardware identified cases that are vulnerable to process variations using dual references. The proposed dual-reference sensing structure has >49% less ML sensing errors than that of the conventional design, leading to a >1.0% accuracy improvement for Fashion MNIST image classification. In addition, owing to the parallel convolution operation of the CAM-based BNN accelerator, the proposed hardware achieved >34% processing-time improvement compared with that of the digital logic implementation.

Compared with traditional images, multispectral images (MSIs) contain more spectral bands and higher data dimensions. The existing MSI classification model has high computational complexity and consumes a lot of computing resources. In this letter, we propose a lightweight multispectral classification method named CABNN based on binary neural networks (BNNs) to effectively have a trade-off between model performance and computational cost. First, we modify and binarize the MobileNetV1 network and add almost computation-free shortcuts to enhance the expressive capability. Secondly, since the BNN is sensitive to the distribution of activation functions, we introduce RPReLU with learnable coefficients to automatically adjust activation distribution at almost no extra cost. Lastly, considering that MSIs have multiple channels, we utilize an efficient channel attention (ECA) module to assign different weights to each channel to concentrate on crucial features and suppress insignificant features. We conduct experiments on four public MSI datasets, including NaSC-TG2, EuroSAT, GID Fine land-cover classification, and UC Merced Land Use. Extensive experiments demonstrate that the proposed CABNN has higher efficiency and better comprehensive performance than the state-of-the-art methods across the board.

An efficient unconstrained facial expression recognition algorithm based on Stack Binarized Auto-encoders and Binarized Neural Networks

Deep Neural Networks (DNNs) are very powerful and successful but suffer from high computation and memory cost. As a useful attempt, binary neural networks represent weights and activations with binary values, which can significantly reduce resource consumption. However, the simultaneous binarization introduces the coupling effect, aggravating the difficulty of training. In this paper, we develop a novel framework named TP-ADMM that decouples the binarization process into two iteratively optimized stages. Firstly, we propose an improved target propagation method to optimize the network with binary activations in a more stable format. Secondly, we apply the alternating direction method (ADMM) with a varying penalty to get the weights binarized, making weights binarization a discretely constrained optimization problem. Experiments on three public datasets for image classification show that the proposed method outperforms the existing methods.

Binary Neural Networks (BNNs) are regarded as very effective approaches to reduce the high computational and memory cost of deep convolutional neural networks; however, most of the previous works only focus on the binarization of traditional large-scale networks. In this paper, to further decrease the computational and memory complexity, we propose to binarize the lightweight network: GhostNet, which can generate feature maps with fewer operations. We first modify the ghost block for reducing the information loss caused by the binarization. Moreover, to enhance the performance of binarized GhostNet, some training schemes are introduced including gradient approximation and new activation layers. Various experiments on CIFAR10 dataset show that, compared with other methods, the MicroNet can achieve better performance with fewer computational and memory cost.

This paper presents the development of a ship-detecting edge-processing system for deployment on an aerial FPGA platform. A ship detection chain was developed with imager-specific pre-processing algorithms, massively parallel FPGA neural network inference, and host post-processing procedures. The ship detection binary neural network implemented in combinational logic enables high frame and detection rates, and achieves 98.40% patch classification accuracy. A new algorithm for optimizing a combinational binary neural network circuit is presented that merges multiple neurons in a network layer taking advantage of similarities between neuron weights, which leads to lower logic size and power consumption. Thus, state-of-the-art performance is achieved in comparison to similar previous works using combinational binary neural networks, achieving 38 ns inference latency, 0.425 W of power dissipation, and only 19 k FPGA slices.

In the era of Artificial Intelligence (AI), bio-inspired perceptual computing system design brings favorable opportunities, while still facing considerable challenges in the meantime. Especially for tasks of image recognition in power-limited vision-based Internet of Things (IoT) devices, energy constraints due to the end of Dennard scaling limit the performance of Neural Network (NN) algorithms on popular digital platforms, which would not reach the energy efficiency requirement for embedded AI applications. In this paper, a processing near sensor architecture in mixed-signal domain with CMOS Image Sensor (CIS) of convolutional-kernel-readout method is proposed. Visual data is collected from a smart CIS, which can realize maximum 5 × 5 kernel-readout with minimum one slide step for convolutional operations. The outputs of CIS are directly processed by analog processing units locating near CIS without the constraint of digital clock and bottleneck of Analog-to-Digital Converter (ADC). By analyzing the effects of analog noise on classification accuracy, we further evaluate the fault-tolerance of the system to circuit noise and the device imperfection, such as mismatch and process variation. A mixed-signal visual perception chip is fabricated with a 32 × 32 image sensor and a Binarized Neural Network (BNN) processing array integrated with SMIC 180nm standard CMOS mixed-signal process. Measurement results show up to 545.4 GOPS/W energy efficiency with 1.8mW power consumption taking the advantages of ADC-free processing architecture. This work provides a promising alternative for low-power vision-based IoT intelligent applications.

In pulsed Doppler (PD) radar, active jamming recognition faces two key challenges: complex jamming in scenarios with moving targets and the inefficiency of full‐precision (FP) convolutional neural networks (CNNs) for deployment. This letter proposes a binary pyramid self‐supervised reconstruction network (BPSR‐Net), a lightweight recognition algorithm based on binary neural networks (BNNs). BPSR‐Net employs a piecewise quadratic gradient approximation (PQGA) to improve training stability, a multi‐scale binary pyramid (BiPy) structure for efficient feature extraction, and a binary self‐supervised reconstruction (BiSR) module to enhance global feature learning. Experiments on 12 single and compound jamming types show that BPSR‐Net achieves 98.93% top‐1 accuracy, 99.90% top‐5 accuracy, with only 15.64 Mbit of memory usage and 43.76 × 10 6 FLOPs. The proposed model balances accuracy, memory, and computational cost, providing a practical solution for low‐power radar anti‐jamming systems.