XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults

With the increased densities of integrated circuits, several different types of faults can occur. Faults in digital circuits resulting from random defects can introduce DC (stuck-at) faults as well as AC (delay) faults. Previous work in statistical modeling and analysis for delay fault testing generally assumes that at most a single delay fault can occur along any given path in the circuit under test. In this paper we investigate the statistical effect of multiple delay faults along any path in a circuit under test, and predict the path delay fault probabilities as well as the maximum number of path delay faults for both combinational and sequential benchmark circuits. We begin with the development of a statistical model for path delay faults in VLSI circuits [4], which takes into account multiple delay faults along any signal path.

An efficient delay test generation (DTEST GEN) system for combinational logic circuits is presented. In the DTEST GEN system, delay testing problems are divided into gross delay faults and small delay faults separately so that the tradeoff between the levels of delay testing effort and the confidence levels of proper system operation can be explored. Complete automatic test pattern generation (ATPG) algorithms are proposed for both gross delay faults and small delay faults. A novel timing analysis method for delay test generation which uses a conventional depth-first search technique and a novel functionality analysis technique is introduced. The functionality analysis technique examines, necessary conditions for a given delay fault to be testable and estimates the upper bound of the good circuit propagation delay of the longest sensitizable path passing through the fault site. Several benchmark results are demonstrated for both gross delay fault testing and small delay fault testing. >

Recent research results, have shown that the traditional structural testing for, delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults that are untestable in the functional mode while testable in the test mode. This paper presents a pseudo-functional test methodology that attempts to minimize the over-testing problem of the scan-based circuits for the delay faults. The first pattern of a two-pattern test is still delivered by scan in the test mode but the pattern is generated in such a way that it does not violate the functional constraints extracted from the functional logic. In this paper, we use a SAT solver to extract a set of functional constraints which consists of illegal states and internal signal correlation. Along with the functional justification (also called broad-side) test application scheme, the functional constraints are imposed to a commercial delay-fault ATPG tool to generate pseudo-functional delay tests. The experimental results indicate that the percentage of untestable delay faults is non-trivial for many circuits which support the hypothesis of the over-testing problem in delay testing. The results also indicate the effectiveness of the proposed constraint extraction method.

Testing delay faults is becoming critical in new deep submicron digital circuits. This paper introduces a new technique for delay and stuck-at fault testing in digital integrated circuits. The proposed technique consists of sensitizing a path in the digital circuit under test and then incorporating it in a ring oscillator to test for delay and stuck-at faults in the path. This procedure should be exercised for all or at least critical paths in the circuit. To establish oscillations, we should make sure that there is an odd number of inverters in the loop. This technique can be used along with scan techniques or be implemented as a built-in self-test technique. Benchmark results confirm the efficiency of the proposed technique. The technique has been implemented in practice for an an 8-bit digital adder on a field programmable device.

Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these models are not efficient to use in delay tests for large circuits. In this article, we propose a physically realistic yet economical resistive bridge fault model to model delay faults as well as logic faults. An accurate yet simple delay calculation method is proposed. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG. Our fault simulation results show the benefit of at-speed tests.

The quality of a delay test set hinges not only on test patterns and the distribution of the delay defects but on the variations in process parameters as well. Process variations result in the same delay test set displaying differences from die to die in the detection of particular delay defects at the identical circuit node. The application of an identical test set to all devices independent of process variations consequently results in delivering inefficiencies in test time utilization. This paper proposes a delay test technique that adaptively changes the size of the test set based on the position of the device in the process variation space in order to maximize test quality within a given test time.

We investigate two strategies to guarantee temporal correctness of a combinational circuit. We first propose a new technique to identify and test primitive faults. A primitive fault is a path delay fault that has to be tested to guarantee the performance of the circuit. Primitive faults can consist of single- (SPDF's) or multiple path delay faults (MPDF's). Testing strategies for single primitive faults exist. In this paper, we focus on identifying and testing multiple primitive faults. Identification and testing of these faults is important for at least two reasons: (1) a large percentage of paths in production circuits remain untestable under the SPDF model, and (2) distributed manufacturing defects usually adversely affect more than one path and these defects can be detected only by analyzing multiple affected paths. The SPDF's contained in a multiple primitive fault have to merge at some gate(s). Our methodology can quickly (1) rule out a large number of gates as possible merging gates for primitive faults, and (2) prune the combinations of paths that can never belong to any primitive fault. Our identification procedure also finds a test for the fault. We present a complete algorithm for identifying and testing double path delay faults, Identifying and testing all primitive faults is impractical for large designs. This is because no efficient methods are known for testing primitive faults that include a large number of paths. However, to guarantee that the performance of a digital circuit is not affected by timing defects, it is necessary to test all primitive faults. Our second contribution is a new design for testability method. Our method guarantees that only primitive faults with at most two paths can exist in the circuit in the test mode. The main idea is to efficiently identify a small set of signals for inserting test points to eliminate primitive faults with more than two paths. Our test points only provide controllability. Addition of a single test point can lower the cardinality of several primitive faults. Our approach efficiently re-evaluates primitive delay fault testability of the circuit after insertion of a test point. After a few iterations only primitive faults with at most two paths can exist in the circuit in the test mode. Experimental results on several multilevel combinational benchmark circuits are included to demonstrate the usefulness of our techniques.

The author presents a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at-fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. Faults for which no delay test sequence exists are termed sequentially delay redundant. The author describes means of eliminating sequential delay redundancies in logic circuits. He presents a partial-scan methodology for enhancing the testability of difficult-to-test or untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. It is shown that an intimate relationship exists between state assignment and delay testability of a sequential machine. A state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability is described. Preliminary experimental results using the test generation, partial-scan, and synthesis algorithms are presented. >

Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two-pattern testing. Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing. Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs. >

In this paper we investigate methods to detect delay faults in circuits that use standard scan design. We demonstrate that delay faults at several sites in a circuit cannot be detected using standard launch off capture and launch off shift tests that use two test cycles. However, faults at these sites are detectable using tests that use more than two test cycles. Experimental results on benchmark and industrial circuits that use standard scan design show that substantial numbers of transition delay faults require tests using more than one fault activation cycles to detect them.

We describe a method of identifying a set of target crosstalk faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines, using topological and timing information, to deduce a set of target crosstalk faults. In this process, our method also identifies the false crosstalk faults that need not (and/or cannot) be tested in synchronous sequential circuits. Experimental results for ISCAS'89 and ITC'99 benchmark circuits show that the proposed method is CPU time efficient in obtaining the reduced lists of the target crosstalk faults. Also, the lists of the target crosstalk faults obtained by our method are substantially smaller than the sets of all possible combinations of faults.

Path delay fault model is the most suitable model for detecting distributed manufacturing defects which can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability of many practical designs is very low. In this paper we show how to resynthesize a combinational circuit in order to reduce the total number of paths in the circuit. Our results show that it is possible to obtain circuits with a significant reduction in the number of paths while not increasing area and/or delay of the longest sensitizable path in the circuit. Research on path delay testing shows that in many circuits a large portion of paths does not have a test that can guarantee detection of a delay fault. The path delay testability of a circuit would increase if the number of such paths is reduced. We show that addition of a small number of test points into the circuit can help reducing the number of such paths in the given design.

In this paper, we propose a new methodology for diagnosis of delay defects in the deep sub micron domain. The key difference between our diagnosis framework and other traditional diagnosis methods lies in our assumptions of the statistical circuit timing and the statistical delay defect size. Due to the statistical nature of the problem, achieving 100% diagnosis resolution cannot be guaranteed. To enhance diagnosis resolution, we propose a 3-phase diagnosis methodology. In the first phase, our goal is to quickly identify a set of candidate suspect faults that are most likely to cause the failing behavior based on logic constraints. In the second phase, we obtain a much smaller suspect fault set by applying a novel diagnosis algorithm that can effectively utilize the statistical timing information based upon a single defect assumption. In the third phase, our goal is to apply additional fine-tuned patterns to successfully narrow down to more exact suspect defect locations. Using a statistical timing analysis framework, we demonstrate the effectiveness of the proposed methodology for delay defect diagnosis, and discuss experimental results based on benchmark circuits.

Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay fault testing requires the application of scan justified test vector pairs, coupled with careful ordering of the scan flip-flops and/or insertion of dummy flip-flops in the scan chain. Previous works on scan synthesis for path delay fault testing using scan shifting have focused exclusively on maximizing fault coverage and/or minimizing the number of dummy flip-flops, but have disregarded the scan wire-length overhead. In this paper we consider both dummy flip-flop and wirelength costs, and focus on post-layout formulations that capture the achievable tradeoffs between these costs and delay fault coverage in scan chain synthesis.

Existing delay test generation techniques focus on test generation for combinational blocks, and assume the inputs and outputs of the block to be unconstrained. Test application for delay tests is done by means of enhanced scan, scan shifting or functional justification; all these techniques impose minimal constraints on the inputs and the outputs of the combinational block targeted. This leads to over-testing the components for delay defects. This paper analyzes the gains associated with determining the multi-cycle (sequential) sensitization of delay tests. The advantages of determining multi-cycle sensitization is then illustrated on benchmark designs with and without a delay-specific fault model.