The Internet of Things (IoT) enables everyday objects to connect and communicate remotely, transforming areas such as smart homes and industrial automation. A key application is Energy Monitoring Systems (EMS), which track energy consumption and production within houses and communities. Digital Twins (DT) is a growing concept that allows the management and visualization of physical systems via an equivalent digital system. Designing and integrating DTs remains complex and are usually provided as generic approaches that provide more complexity than desired by an expert in the area of EMS. In this paper we provide an approach that allows the design of EMS and the automatic deployment of a Digital Twin instance. The approach automatically connects a physical (or simulated) system to its Digital Shadow counterpart, and provides management and visualization support via a set of tools. We provide a demonstration of the development phase and how the tools are used to manage the deployed system.

This paper is a summary of the presentation at the 2024 Ada-Europe International Conference Ada Developers Workshop. A recent posting of a wishlist requested ''Scope-based files''. Controlled I/O is a response to that request.

Alire (from Ada Library Repository) is an open source package manager for the Ada and SPARK programming languages. Alire indexes projects in source form, but also binary toolchains ready for use from the GNAT compiler suite. Thus, starting a project with multiple dependencies and using a variety of native or cross-compilers becomes straightforward. This short paper discusses the most relevant new features in its 2.0 release, published in March 2024.

1 A rather strange introduction I confess, I am a voracious book reader, and being (luckily) versed in quite a few tongues, I enjoy reading books frequently (but not always) without needing translation. In fact, I find languages fascinating, for all they say about people's culture, history, and traits. As a student in Computer Science in the late 1980s, I was imbued with Noam Chomsky's linguistic ''generative grammar'' theory. That theory sees specific languages as second-order derivatives of a single universal grammar, innate in the human mind. That theory, with its hierarchy of formal grammars, has laid the foundation for the theory and practice of language compilers. The principal tenet of Chomsky's theory is that grammar precedes language.

It is common to translate a programming language to an intermediate representation as part of interpreting or compiling a program written in the language. The question is what are the implications when we try to implement normally unsafe features, such as pointers into a heap with user-controlled deallocation, on top of a virtual machine based on an intermediate language that is inherently safe and provides no user-controlled deallocation. A similar question arises in the implementation of exceptions on top of a virtual machine that has no direct support for exceptions but has lightweight threading. This paper will describe how we are addressing these two challenges as part of building an Ada implementation on top of a parallel virtual machine, and evaluate the result.

The performance of shared-resource multi-core hardware platforms in complex cyber-physical systems (CPSs), e.g., automotive industry, can be improved using task-based parallelism through OpenMP. However, most CPS require certain level of predictability, which challenges the efficient implementation of the task-to-thread mapping process. This exploratory work build on the fact that existing mapping methods mostly use elementary or heuristic algorithms, and the idea that artificial intelligence (AI) algorithms can be used to enhance the efficiency of such processes. Accordingly, this paper (1) evaluates the suitability of AI-based techniques in improving the performance of task-to-thread mapping in the OpenMP framework, and (2) proposes a hypothesis to perform an intelligent mapping using fuzzy logic for multi-queue schedulers to improve the predictability of the system.

Traditional embedded Real-Time Operating Systems (RTOS) or Basic Software (BSW) implementations typically require manual porting to new hardware platforms. However, this approach can be time-consuming and error-prone, especially given the frequent introduction of new or upgraded hardware architectures. In addition, traditional testing methods may not fully capture the complexity and nuances of the system, making it difficult to ensure correctness and dependability. To address these challenges, we propose a comprehensive methodology that integrates formal methods, a WCET tool, and a code generation technique. We use formal methods to create models and verify their correctness against functional and non-functional specifications or properties such as safety, liveness, and timing. We use the WCET tool as a microarchitecture analyzer to analyze the low-level binary code. The intermediate results of the tool are used to verify the correctness of the software implementation against the runtime effects of the hardware, such as data/memory race conditions. Finally, the code is generated from the formal models. Our proposed framework simplifies the maintenance of RTOS or BSW implementations while ensuring their correctness and partially automating portability to new hardware architectures.

LAMP is an introspective analysis and processing framework for AADL. With LAMP, exploration, verification, transformation or any other processing rules are directly embedded inside the AADL model as annex subclauses. LAMP is based on the underlying LMP (Logic Model Processing) technology that itself leverages the Prolog language and a Prolog inference engine. This paper illustrates the use of LAMP by five practical use cases addressing some of the most important design issues in critical real-time software development.

The Architecture Analysis and Design Language (AADL) is a SAE standard for modeling both hardware and software architecture of embedded systems. Widely embraced by stakeholders in critical real-time embedded systems, the AADL standard is used to address a large set of concerns including performances (latency, schedulability), safety, and security. The ADEPT workshop aims to present and report on current projects in the field of design, implementation, and verification of critical real-time embedded systems where AADL is a first-citizen technology. This article is a summary of the second edition of the workshop in 2023.

This article deals with scheduling anomalies in real-time systems. We present MONANO, a POSIX user-level library allowing applications to dynamically detect a preidentified set of real-time scheduling anomalies. The MONANO library is based on the modelling of architecture and runtime constraints. MONANO monitors during the runtime the timing behavior of the application and deduces properties needed to identify scheduling anomalies. We present also a benchmark to evaluate our approach. The benchmark is composed of several programs implementing the most frequent real-time scheduling anomalies.