Current Approximate Graph Pattern Mining (AGPM) systems rely on uniform and static sampler allocation strategies, which result in significant computational redundancy because most regions of the sampling space contribute little to the final estimate. However, existing systems overlook this critical characteristic and fail to account for the hierarchical memory architecture of modern servers, leading to slow convergence and substantial memory access overhead. To address these challenges, we propose HierMine, a novel AGPM system designed to overcome the aforementioned drawbacks. The core contributions of HierMine include: (i) a hierarchical sampling strategy that minimizes redundant computation and accelerates convergence; (ii) a dynamic sampling adjustment mechanism that partitions the sampling space online and reallocates samplers adaptively to enhance the hierarchical strategy; (iii) an online grouping-based convergence detection technique that enables the fine-grained dynamic sampling adjustment mechanism; and (iv) a hierarchical data layout optimized for memory access efficiency. Extensive experiments show that HierMine delivers an average speedup of up to 28.9 × over state-of-the-art AGPM systems such as ScaleGPM, while maintaining strong theoretical guarantees on estimation quality. It also consistently outperforms exact graph pattern mining systems, highlighting the practical benefits of our approximate approach.

With the advancement of GPU architecture, matrix computation engines such as NVIDIA Tensor Cores now support double-precision (FP64) General matrix multiplications (GEMMs) with the same efficiency as single-precision (FP32) GEMMs. However, the adoption of this enhanced FP64 capability remains limited, primarily restricted to applications that involve multiple FP64 BLAS3 operations. Singular Value Decomposition (SVD), a fundamental decomposition in numerical linear algebra with numerous applications, can greatly benefit from exploiting this hardware feature. In this article, for FP32 SVD, we propose a novel algorithm, FP64 precision eigenvalue decomposition (EVD) based SVD, specifically designed to leverage the latest GPU architectural features. We provide a theoretical analysis demonstrating the feasibility of our approach on emerging GPU architectures and evaluate it from both accuracy and performance perspectives. Moreover, for FP64 SVD, we introduce a double-blocking band reduction technique combined with a GPU-based bulge chasing algorithm to further accelerate the overall SVD process. Experimental results show that, for FP32 SVD, our EVD-based SVD implementation achieves higher numerical accuracy and delivers speedups of up to 6.1× on H100 and 5.0× on A100 over the state-of-the-art cuSOLVER SVD solver. In the case of FP64 SVD, our method also achieves 4.9× and 4.8× speedups on H100 and A100, respectively. These results highlight the potential of our approach as a highly efficient and accurate solution for SVD on modern GPU platforms.

Efficient sampled simulation of multi-threaded applications remains a long-standing challenge with significant implications for evaluating modern computing systems. Existing methodologies are either limited in speedup (Time-based Sampling) or restricted to specific synchronization types (BarrierPoint). Workload-specific techniques tend to be rigid with respect to region selection, which may limit the overall speedup. In this work, we aim to solve these challenges and propose a novel sampling technique for multi-threaded applications, called LoopPoint, that is both agnostic to the type of synchronization primitives used and scales with the similarity exhibited by the application. The methodology combines several vital features, including (a) repeatable, up-front loop-based analysis of the workload, (b) a novel clustering approach to take into account run-time parallelism, and (c) the use of simulation markers to divide the execution into measurable chunks based on the amount of work done, even in the presence of spin-loops. LoopPoint identifies representative regions that can be simulated in parallel to achieve speedups of up to 801 × for the train input set of the multi-threaded SPEC CPU2017 benchmarks with an absolute geometric mean sampling error of just 1.48%. For the ref inputs, we estimate speedups up to 31,253 ×, demonstrating how the identification of application regularity and loops can lead to significant simulation improvements. We further propose ROIperf, a hardware-based framework to enable rapid correlation of representative regions. Instead of long-running simulations, ROIperf allows for the performance measurement of full workloads and the representative regions directly on the hardware itself. This presents a practical methodology for large, realistic workloads where the prevailing simulation-based validation techniques are prohibitively slow. We demonstrate the efficacy of ROIperf across SPEC CPU2017 and NPB benchmark suites, showing strong correlation between hardware measurements and simulation predictions.

FPGAs have become key players in data-centers. However, the integration of such accelerators poses several challenges related to Quality of Service (QoS). Herein we propose a compiler-based toolchain that increases FPGA flexibility by enabling dynamic stateful HW-SW migration. Task migration is instrumental in solving at least fault-tolerance and preemption in FPGA. Thus, we design, based on our toolchain, a checkpointing-rollback framework to enable restoring a task after a component failure (i.e., FPGA crash) and making a first step toward fault-tolerant data-center systems. Starting from the Xilinx HLS compilation workflow, we design 1) a set of LLVM optimization passes that instrument an FPGA-accelerated application with migration points, and 2) an asynchronous periodic data backup scheme for efficient context transfers. These together allow the FPGA-accelerated task to migrate statefully from the FPGA onto its host CPU where execution is resumed. We evaluate this proposal on several applications and show that, although reliability (inevitably) comes at a cost, our framework offers promising results by transforming a set of common benchmark kernels into fault-tolerant kernels with acceptable best-case runtime overheads (e.g., 1.1x for Gaussian Blur filter and MaxPool operation). We also show that FPGA task preemption allows HW-SW multitasking.

Multi-tenant clouds enhance resource sharing among Virtual Machines (VMs) to boost overall utilization and reduce power consumption. However, this also introduces interference among workloads from different tenants and impedes VM performance isolation. In this paper, we first demonstrate that the last-level cache (LLC) in CPUs, which is inherently shared by all VMs on the same physical machine, becomes a significant contending resource for LLC-critical workloads, leading to notable performance imbalances under the default hardware caching strategy. Although recent studies on LLC scheduling have progressed, they often require detailed profiling of user workloads or rely on hyperparameter tuning, limiting their applicability to private clusters or specific scenarios. We propose SpiderSense, a software-initiated LLC partitioner for managing Virtual Machine Monitors (VMM), to address these limitations. SpiderSense leverages modern yet off-the-shelf server CPU features to adaptively orchestrate LLC allocation among running black-boxed user VMs. SpiderSense dynamically samples VMs and calculates their fair share of LLC to allocate them while fully improving performance isolation among VMs. We experiment with SpiderSense using typical LLC-critical workloads, representative of the types of applications that stress LLC performance, such as Memcached and Llama. Our results show that SpiderSense improves performance by up to 40% in numerous colocation scenarios compared to current solutions.

This is a corrigendum for the article “gECC: A GPU-based high-throughput framework for Elliptic Curve Cryptography” published in ACM Trans. Arch. Code Optim. 22, 3, Article 84 (September 2025), 27 pages.

Heterogeneous platforms combining CPUs and DSPs offer the potential for energy-efficient computing but are difficult to program. OpenCL enables code portability across processors but does not guarantee performance portability on DSPs due to the unique challenges in barrier synchronization and local memory management. This article introduces OctoCL , a compiler-based framework that addresses these challenges through two key optimizations: (1) a recomputation-based variable expansion technique to reduce barrier synchronization overhead, and (2) automatic merging of memory access patterns into DSP-DMA operations for efficient data transfers. We evaluate OctoCL using 18 OpenCL benchmarks from the Parboil and Rodinia suites. Experimental results show that OctoCL achieves an average speedup of 1.46× (up to 3.36×) over the baseline OpenCL compiler on the FT-M7032 CPU-DSP platform. These optimizations enhance performance portability while preserving backward compatibility, requiring no manual code modifications.

As high-performance computing (HPC) systems continue to grow in scale and complexity, simulation has emerged as a crucial tool for evaluating network performance, especially when real hardware is unavailable. However, achieving highly accurate results quickly and with low overhead in large-scale network evaluations remains a significant challenge. To tackle this issue, we propose SimHost, a lightweight end-to-end offline simulation framework featuring flexible communication and host models tailored for large-scale network simulations. SimHost enables the replay of application communication events without requiring an actual or virtualized execution environment or hardware. It accurately restores the message passing and system processing overheads of real application execution, delivering evaluation results consistent with physical deployments. With its cross-platform and discrete event design, SimHost integrates seamlessly with existing simulators, needing only minimal modifications for synchronous operation. Evaluations and use cases confirm that SimHost’s workloads accurately replicate real-world scenarios. Experimental results indicate that SimHost achieves less than 5.12% error in application completion time compared to the testbed, while maintaining only 7% simulation runtime overhead when scaled to 2048 nodes relative to synthetic workloads.

Nowadays, Graphics Processing Units (GPUs) dominate in a wide spectrum of computing realms with massive parallel processing capabilities. However, as resources are continuously integrated into GPUs, traditional serial execution often leads to underutilization. Prior studies have shown that allowing multiple kernels to run concurrently and share GPU resources can effectively improve both resource utilization and system throughput. Nonetheless, existing methods for solely automating concurrent kernel execution either schedule kernels within individual applications (i.e., kernel-level) or enable task concurrency across multiple applications (i.e., task-level), thus leaving substantial GPU capacity underexploited. Moreover, they inevitably introduce new programming frameworks, which incur cumbersome manual efforts and further impose substantial programming burdens on developers. To address these limitations, we propose HuntKTm , a hybrid scheduling and automatic management method that cooperates kernel-level and task-level concurrency to enhance system throughput with minimal code modification. Specifically, HuntKTm comprises a stream scheduler to assign kernels, a task scheduler to dispatch tasks onto GPUs, and a memory manager to reduce memory footprint. The stream scheduler applies a strategy to dispatch kernels to hardware queues and adopts a novel algorithm to remove redundant synchronizations in computational flow. Then, the task scheduler automatically issues tasks based on resource requirements and availability to support GPU sharing among uncooperative applications. Finally, the memory manager reduces memory footprint for tasks by limiting the lifetimes of memory objects, which thereby enables more tasks to execute simultaneously. Experimental results demonstrate that HuntKTm improves system throughput by 33.2% over the existing state-of-the-art CASE framework on a single machine equipped with four NVIDIA A100 GPUs and reaches 13.8% higher application-level performance over Taskflow, even with lessened programming efforts.

Building LSM-Tree-based key-value stores (LSM stores) on Cloud Block Storage (CBS) is becoming increasingly popular due to its convenience compared to local block storage devices. However, the constrained bandwidth of CBS and the competition between bandwidth and paid IOPS results in performance degradation and high tail latency in LSM stores, which cannot provide stable service-level agreements (SLAs). We propose RaKV, an efficient LSM store with stable SLAs for CBS, to improve write performance and reduce latency. This store successfully tackles challenges by utilizing instance memory and managing data flow between components. First, RaKV designs a dynamically partitioned L 0 placed in memory and a parallel L 0 - L 1 compaction mechanism to minimize write amplification and write stalls, mitigating the performance impact of the CBS’s constrained bandwidth. Second, RaKV proposes a bandwidth-aware admission control mechanism that dynamically adjusts the number of incoming user requests based on the capacity of the L 0 layer and the available cloud storage bandwidth, thus preventing write stalls and ensuring SLA consistency. Finally, RaKV implements an efficient read/write I/O isolation and scheduling mechanism to coordinate bandwidth and IOPS demands, thus stabilizing read SLAs and reducing read latency. Our evaluation results show that RaKV improves random write performance by 25.8% compared to the state-of-the-art key-value store ADOC, with more consistent throughput and lower read latency than CruiseDB.