The performance enhancements of coarse-grain reconfigurable cryptographic arrays (CGRCAs) through technology upgrades and increasing chip size are approaching limits. Enhancing parallel processing capabilities can relieve the computational burden on CGRCA in high-density computing scenarios. Specifically, a novel parallel processing approach is introduced in this paper, named virtual heterogeneous multi-core pipelining (VHMP). VHMP supports virtual heterogeneous multi-core and intra-core multitask pipelining. Informed by hardware virtualization principles and analysis of CGRCA architectures, VHMP constructs virtual computing cores (VCCs) on CGRCA using multi-launch pipelines and implements multitask interleave pipelines within each VCC, enabling parallel processing at pipeline, task, and instruction levels. Furthermore, a hierarchical control mechanism is embedded within VHMP, integrating virtual computing path level and task-level management. This control mechanism allows diverse cryptographic algorithms to run concurrently without being bound to specific types or modes. Finally, applying VHMP to a 32 × 4 CGRCA, 32 heterogeneous VCCs are instantiated, with each core handling up to 16 interleaved tasks. Compared to treating CGRCA as a homogeneous multi-core processor, the VHMP approach achieves an average acceleration of 4.33 × (up to 6.34 ×) with quadrupled instruction execution capability. Additionally, the control mechanism reduces context volume to 18.7% and boosts configuration speed by 3 ×. Compared with related architectures, VHMP improves CGRCA throughput by an average of 5.3 ×.

Analog circuit placement is crucial for optimal performance, but achieving a decent layout demands expertise and time. Recent advances in machine learning techniques have shown promising results in modeling analog layout performance. PAPlace further extends these methods and integrates them into the core analog placement engine, allowing direct optimization of the post-layout performance effectively. Our approach proposes a differentiable prediction model that combines layout and wiring information into a non-linear analog placement engine. We then incorporate the differentiable performance model into a gradient-descent-based global placement engine. A multi-objective optimization method is further proposed to find the common gradient descent direction for different metrics. The experimental results on benchmarks under the TSMC 40nm technology node demonstrate the superiority of the proposed framework compared with the cutting-edge works, with up to 2163.00μ V , 73.95dB, 62.25MHz, 57.84dB improvement in Offset Voltage, CMRR, BandWidth, DC Gain metrics.

Designing efficient RM strategies is a cornerstone of modern computing, driving innovations in performance optimization, energy efficiency, and security. While simulators have long been the go-to tools for RM research, they fail to balance accuracy and practicality: high-fidelity simulators are excruciatingly slow, and low-fidelity ones compromise on reliability. Real hardware offers unparalleled precision and accuracy but remains underutilized due to significant barriers, including fragmented implementations, lack of portability, and prohibitive development overhead. We present ARDiS, the first open-source 1 and portable framework to provide a unified, architecture-agnostic platform for running system-level resource management (RM) techniques directly on real hardware. ARDiS eliminates the need to “reinvent the wheel,” enabling researchers to design, implement, and evaluate sophisticated RM strategies—including machine learning-based approaches—with minimal effort and maximum reproducibility. To demonstrate its versatility, we evaluate ARDiS on two real-world hardware platforms: a server-grade heterogeneous processor (Intel i9-12900) and a resource-constrained embedded system (NVIDIA Jetson TX2). Through extensive experimentation, we validate the ability of ARDiS to deliver accurate, scalable, and reproducible results across diverse platforms and application domains. By lowering the barriers to hardware-based RM research, ARDiS empowers the design automation community to explore new frontiers in system-level optimization and innovation.

Fine-grained power estimation is fundamental to modern MPSoC design and operation, enabling early power and thermal budgeting before fabrication, predictive thermal control at runtime, post-silicon microarchitectural energy debugging, and hardware security analysis. Existing System-on-Chip (SoC) designs often rely solely on total power consumption measurements because of the cost, size, and complexity of power sensors. However, the lack of precision and granularity in power measurements leads to inefficient power and thermal management and limits the ability to detect failed or compromised sensors. To tackle these challenges, we propose the Improved Clustering Blind Power Identification (ICBPI) approach, an innovative approach for fine-grained power estimation in SoCs. ICBPI leverages total power measurements and per-unit temperature data, even with potentially unreliable sensors, to deliver accurate per-unit power estimates. This dual focus not only enhances power estimation, leading to better power management decisions, but also improves the detection of malicious sensors—such as those compromised by hardware Trojan attacks—that manipulate sensor data to induce potential system failures. Extensive evaluations across four SoC architectures demonstrate ICBPI’s superior performance in reducing per-core power estimation errors by \({77.56\%} \) compared to the baseline Blind Power Identification (BPI) and by \({68.44\%} \) compared to the state-of-the-art approaches. Furthermore, ICBPI achieves \({100\%} \) detection of malicious thermal sensor attacks and enhances the localization process compared to the Blind Identification Countermeasure (BIC) approach. In the comparative analysis between ICBPI and the most recent model, Alternating Blind Power Identification (ABPI), ICBPI shows error rates as low as \({0.5\%} \) compared to \({2.8\%} \) in a 2 × 2 mesh benchmark and outperforms ABPI on heterogeneous architectures. The NVIDIA Jetson Xavier AGX development board serves as a platform for validating ICBPI. Consequently, ICBPI demonstrates an approximate reduction in average error of \(79.71\% \) on the CPU and \(79.59\% \) on the GPU relative to three existing state-of-the-art approaches.

Large language models (LLMs) have been the driving force behind significant advancements in artificial intelligence. However, their unique self-attention mechanism leads to difficulties in accelerating the inference. Softmax, with its complex nonlinear operations and low parallelism, significantly limits the efficiency of LLMs for long sequences. This work proposes a novel high-parallelism hardware/software co-design Softmax solution. By incorporating a sum estimation algorithm, we eliminate the need for complex exponential on all elements. A high-speed low-energy hardware architecture is introduced by applying high-parallelism statistical module and simplified division module. Experimental results demonstrate that our approach achieves a 9.90%-44.75% reduction in latency and up to a 17.36% reduction in energy consumption compared to state-of-the-art Softmax hardware, with minimal impact on model inference accuracy.

Ensuring the functional correctness of a digital system is achievable through formal verification. Despite the increased complexity of modern systems, formal verification still needs to be done in a reasonable time. Hence, Polynomial Formal Verification (PFV) techniques are being explored, as they provide guaranteed polynomial upper bounds on the time and space required for the verification process. Recently, it was shown that circuits characterized by a constant cutwidth can be verified in linear time using Answer Set Programming (ASP). However, these results are limited to combinational circuits, whereas most designs used in digital systems are sequential. In this paper, we introduce Linear Formal Verification (LFV) as a subclass of PFV for sequential circuits with constant cutwidth, which are verifiable in linear time and space using ASP. We achieve this by proposing a new data structure called Weighted And-Inverter Graph (W-AIG). Unlike existing formal verification methods, we prove that our approach can verify any sequential circuit with a constant cutwidth in linear time and space. Finally, we implement our approach and experimentally show that a variety of sequential circuits, such as pipelined adders, serial adders, and shift registers, can be verified in linear time and space, while ring counters can be verified in polynomial time and space, confirming our theoretical findings.

Read disturb is a circuit-level noise in high-density solid-state drives (SSDs), which may corrupt existing data in SSD blocks and then cause high read error rates. The approach of read reclaim (RR) is commonly used to avoid read disturb errors by migrating the valid data pages to other free blocks for resetting negative effects of read disturbs, but it affects both I/O responsiveness and SSD lifetime. This paper proposes SWEEP to minimize the number of RR operations. Specifically, it gathers hot read and hot write data pages together, and saves them in a portion of designated blocks. After that, the hot write data pages will be invalidated and the hot read data pages in such blocks are likely to be migrated to other blocks through garbage collection (GC). Consequently, the read disturbs on these hot read data pages will be reset, without additional RR operations. Trace-driven simulation experiments show that our proposal can significantly reduce the number of RR operations by between 1.6 % and 74.4 %, which contributes to a maximum reduction of 29.7 % on total erase operations, indicating a better lifetime of SSD devices. In addition, it can reduce the overall I/O response time by up to 52.9 %, compared to existing optimization schemes for SSDs.

Chiplet-based designs use large numbers of interconnects that need to be tested thoroughly. Standard isolation logic allows the logic blocks (chiplets) and the interconnects to be tested separately. It was recently suggested for additional defect coverage to use a scan-based test set that tests the interconnects together with the logic blocks in a mode of operation that is closer to functional. In this scenario, a scan-based test set for a logic block targets faults in the logic block as well as the interconnects it drives. An exhaustive static fault model was used earlier for subsets of adjacent interconnects. In the same scenario, this article studies the presence of functionally undetectable interconnect faults, and their relationship to the configuration of the interconnects as a two-dimensional array. The article observes that the specific configuration of the interconnects in the two-dimensional array can affect the number of functionally undetectable faults. Moreover, by modifying the configuration, it is possible to eliminate functionally undetectable faults that are important to consider in other configurations. The article describes a test generation procedure that includes the identification of functionally undetectable interconnect faults, and a procedure for reconfiguring the interconnects to eliminate undetectable faults. The implementation of the procedures was carried out in an academic simulation environment. Experimental results for benchmark circuits demonstrate the effectiveness of the procedures in achieving complete interconnect fault coverage, and eliminating all the undetectable interconnect faults.

Face-to-face (F2F) stacked three-dimensional (3D) IC is a promising alternative for scaling beyond Moore’s Law. In F2F 3D ICs, dies are connected through bonding terminals whose positions can significantly impact routing performance. Further, there exists resource competition among all the 3D nets due to the constrained bonding terminal number. In advanced technology nodes, traditional bonding terminal planning may also introduce legality challenges of bonding terminals, as the metal pitches can be much smaller than the sizes of bonding terminals. Previous works attempt to insert bonding terminals automatically using existing 2D commercial P&R tools and then consider interdie connection legality, but they fail to take the legality and routing performance into account simultaneously. In this article, we provide a novel bonding terminal assignment formulation for effective routing-aware bonding terminal planning. We explore the generalized assignment formulation and provide the routability guidance in our hybrid bonding terminal assignment problem. Our framework, BTAssign , offers a strict legality guarantee and an iterative solution. We provide two versions of the BTAssign framework, BTAssign-WL [ 1 ] and BTAssign-R, which BTAssign-R extends BTAssign-WL [ 1 ] by considering routability. The experiments are conducted on 18 open source designs with various 3D net densities and the most advanced bonding scale. The results reveal that all the testing cases with different partitioning and placement strategies could gain benefits from our BTAssign framework.

This article introduces GenPart 2.0, an enhanced version of the hypergraph partitioner GenPart. While GenPart was limited to handling only unit vertex weights, GenPart 2.0 extends capabilities to include varying vertex weights. This extension is achieved through a variational graph neural network-based generative model and new feature preparation techniques. GenPart 2.0 addresses hypergraph partitioning challenges by establishing an embedding space that adheres to normalized cut and balance constraints. The generative model in GenPart 2.0 is designed to explore various partitioning configurations within this embedding space. Further, it enhances partitioning solutions using the V-cycle method. Testing on VLSI circuit benchmarks, including ISPD98, ISPD2005, and Titan23, under various balance constraints, has demonstrated improved performance by GenPart 2.0.