Purpose Gallium nitride high electron mobility transistors (GaN HEMTs) are representative wide-bandgap semiconductor devices characterized by their superior high-frequency switching characteristics. This paper aims to review their modeling methods and drive control technologies, systematically summarize the research progress and predict the future development trends. Design/methodology/approach This paper first introduces the background and advantages of GaN HEMTs and then reviews four modeling methods: physical model, behavioral model, analytical model and hybrid model. It also summarizes their respective characteristics and application scopes. Furthermore, key drive control techniques are discussed in depth. Finally, the development trend of modeling technology is predicted by combining the characteristics of typical devices. Findings Switching modeling methods for GaN HEMTs have advanced to better address high-frequency and high-power application requirements. Each model type offers distinct advantages regarding accuracy, complexity and physical interpretability. Integrating appropriate drive control strategies further enhances system performance. Originality/value This paper summarizes four switching models for GaN HEMTs and compares their characteristics and applicable scenarios. Subsequently, it further explores the driving characteristics and key technologies of GaN HEMTs, including dead time control, segmented driving and level shifting techniques. Finally, future development trends are discussed in light of practical device effects, with a particular focus on multiphysics coupling, emerging artificial intelligence (AI) modeling and adaptive driving technologies.

PurposeThis paper aims to solve the problems of large hard switching loss and unclear resonant parameter design in the existing inverter power supply topology.Design/methodology/approachThis paper proposes a simple and reliable two-stage isolated inverter composed of series quasi-resonant push-pull and external freewheeling diode full-bridge inverter. The power supply topology is analyzed, the topology mode is analyzed, the mathematical model of the converter is established and the DC gain of the converter is deduced. The relationship between the load and the output gain of the resonant tank is presented, a new resonant parameter design method is proposed, and the parameter design of the resonant element of the converter is clarified.FindingsThe resonant components of the converter are designed according to the proposed resonant parameter design method, and the correctness of the method is verified by simulation and the development and testing of a 500 W experimental prototype. After experimental tests, the peak efficiency of the experimental prototype can reach 94%. Because the experimental prototype achieves soft switching, the heat generation of the switch is greatly reduced, so the heavy heat sink is removed, and the volume is reduced by about 30% compared with the traditional power supply, and the total harmonic distortion of the output voltage is about 2%.Originality/valueThe feasibility of the scheme is verified by experiments, which is of great significance for improving the efficiency of the inverter power supply and parameter optimization.

PurposeThe purpose of this paper is to prevent the destruction of other parts of a wind energy conversion system because of faults, the diagnosis of insulated-gate bipolar transistor (IGBT) faults has become an essential topic of study. Demand for sustainable energy sources has been prompted by rising environmental pollution and energy requirements. Renewable energy has been identified as a viable substitute for conventional fossil fuel energy generation. Because of its rapid installation time and adaptable expenditure for construction scale, wind energy has emerged as a great energy resource. Power converter failure is particularly significant for the reliable operation of wind power conversion systems because it not only has a high yearly fault rate but also a prolonged downtime. The power converters will continue to operate even after the failure, especially the open-circuit fault, endangering their other parts and impairing their functionality.Design/methodology/approachThe most widely used signal processing methods for locating open-switch faults in power devices are the short-time Fourier transform and wavelet transform (WT) – based on time–frequency analysis. To increase their effectiveness, these methods necessitate the intensive use of computational resources. This study suggests a fault detection technique using empirical mode decomposition (EMD) that examines the phase currents from a power inverter. Furthermore, the intrinsic mode function’s relative energy entropy (REE) and simple logical operations are used to locate IGBT open switch failures.FindingsThe presented scheme successfully locates and detects 21 various classes of IGBT faults that could arise in a two-level three-phase voltage source inverter (VSI). To verify the efficacy of the proposed fault diagnosis (FD) scheme, the test is performed under various operating conditions of the power converter and induction motor load. The proposed method outperforms existing FD schemes in the literature in terms of fault coverage and robustness.Originality/valueThis study introduces an EMD–IMF–REE-based FD method for VSIs in wind turbine systems, which enhances the effectiveness and robustness of the FD method.

PurposeA low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.Design/methodology/approachThis paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.FindingsThe proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.Originality/valueThis work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

PurposeThe purpose of this paper is to check the Solar Photovoltaic (PV) inverter working condition with modified unipolar switching pulse. The gate pulse for the inverter switches is generated in MATLAB simulation and interfaced with hardware protype. Simulation results can be compared with hardware results.Design/methodology/approachA considerable amount of research has been done on different Pulse Width Modulation (PWM) techniques. Based on the findings, a modified Unipolar Sinusoidal PWM technique was created with one reference signal and two carrier signals+ (one for the positive half cycle and the other for the negative half cycle) and simulated in the MATLAB/Simulink platform. The prototype inverter module receives the simulated switching pulses via dSPACE DS1104 hardware software interfacing board. The hardware implementation has been done, and the hardware results compared with simulation results for various input voltage levels using resistive load.FindingsThis modified switching pulse has dead band and additional hardware setup is not required. 3-phase multi-level inverter output waveform has been achieved with six switches in this method and with low filter values, pure sine wave output can be obtained in simulation. By this method of switching pulse generation and testing, for every modification in switching pulse hardware gate driver is not required. Resulting time consumption and money investment are lower.Originality/valueModified Unipolar SPWM pulse generation technique is novel method for solar PV inverter. The switching pulse has been designed and tested in both MATLAB/Simulation and hardware prototype inverter. Hardware and software results are identical. This method of pulse generation and hardware implementation has not been done anywhere before.

PurposeThe primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.Design/methodology/approachFirst, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.FindingsThis work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm2 compared to contemporary designs.Originality/valueThe proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

PurposeThe purpose of this study is to eliminate voltage harmonics and instantly measure the positive sequence fundamental voltage during unbalanced grid conditions, the dual second-order generalized integrator-phase locked loop used in series hybrid filter structures is often used in grid synchronisation in three-phase networks. The preferred series active hybrid power filter simultaneously compensates for voltage balancing and current harmonics generated by non-linear loads.Design/methodology/approachThis paper examines the use of renewable energy–based microgrid (MG) to support linear and non-linear loads. It is capable of synchronising with both the utility and the diesel generator unit. Power is transferred from the grid throughout a stable grid situation with minimum renewable energy generation and maximum load demand. It synchronises with diesel generator set to supply the load and form an AC MG during outages and minimum renewable power generation. In islanded and grid-connected mode, the voltage and power quality issues of the MG are controlled by static synchronous compensator and series hybrid filter.FindingsBecause of the presence of non-linear loads, reactive loads in the distribution system and the injection of wind power into the grid integrated system result power quality issues like current harmonics, voltage fluctuations, reactive power demand, etc.Originality/valueThe voltage at the load (linear and non-linear) is regulated, and the power factor and total harmonic distortions were improved with the help of the series hybrid filter.

PurposeThis paper aims to collect the energy consumption data and carry out energy consumption analysis of chemical enterprises, which is helpful to grasp the working conditions of each equipment accurately and to perfect the demand side management (DSM) for the user in the terminal.Design/methodology/approachThe paper proposes a load monitoring system of chemical enterprises to collect the energy consumption data and carry out energy consumption analysis. An Elman neural network based on sparrow search algorithm is proposed to predict the power consumption change and distribution trend of enterprises in the future production cycle. The calculation efficiency and prediction accuracy have been significantly improved.FindingsThe paper analyzes the energy saving effect of energy efficiency management as well as “avoiding peak and filling valley” measures, and reasonable control requirements and assumed conditions are put forward to study the operability of enterprise energy saving measures from the DSM.Research limitations/implicationsBecause of the chosen enterprise data, the prediction accuracy needs to be further improved. Therefore, researchers are encouraged to test the proposed methodology further.Practical implicationsThe paper includes implications for the development of energy consumption analysis and load forecasting of chemical enterprises and perfects the DSM for the user.Originality/valueThis paper fulfills an identified need to study how to forecast the power load and improve the management efficiency of energy consumption.

PurposeThis paper aims to improve the general circuit of driving and protection based on insulated gate bipolar transistor (IGBT) in dielectric barrier discharge power supply by designing a novel half-bridge inverter circuit with discrete components.Design/methodology/approachWith one SG3524 chip, the structure based on discrete components is used to design the IGBT drive circuit. The driving waveform is isolated and sent out by photo-coupler 6N137. The protection circuit is realized by Hall sensor directly detecting the main circuit current, supplemented by a few components, including diodes, resistors, capacitors and triodes. It improves the reliability of the protection circuit.FindingsIn the driving circuit, the phase difference of signals from two channels are 180°. Moreover, when the duty cycle is set at 40%, it can ensure sufficient pulse width modulation response time. In the protection circuit, when over-current occurs, an intermittent output signal is automatically sent out. Furthermore, the over-current response time can be controlled independently. The peak voltage can be adjusted continuously from 0 to 30 kV with its frequency from 8 to 25 kHz and the power output up to 150 W.Originality/valueThe novel circuit of driving and protection makes not only its structure simpler and easier to be realized but also key parameters, such as frequency, the duty cycle and the driving voltage, continuously adjustable. Moreover, the power supply is suitable for other discharges such as corona discharge and jet discharge.

PurposeThe privacy of the information is a major challenge in the communication process. In the present modern generation, the cryptography plays a vital role in providing security for data, such as text, images and video while transmitting from source to destination through internet or intranet. The Rivest-Shamir-Adleman (RSA) is an asymmetric key cryptographic system, where the security of the method works on the strength of the key.Design/methodology/approachIn an asymmetric key crypto system, a pair of keys is generated one public key for encryption and one private key for decryption. The major challenge of implementing the RSA is the power function which becomes tedious and time consuming as the exponential value increases. The Chinese remainder theorem proves to be the best for data encryption when it comes to execution time of the algorithm. The proposed novel RSA algorithm with lookup table (LUT) is an extension to the Chinese remainder algorithm, which works better for image and video in terms of time complexity.FindingsThis paper presents a LUT approach for implementing the RSA with a minimal processing time. The proposed algorithm was compared with the standard algorithms like, Chinese remainder theorem, binary approach and squared multiplication approach. As the size of the exponent value increases, the proposed method shows better performance compared to other standard methods.Originality/valueThis paper presents a LUT approach for implementing the RSA with a minimal processing time. The proposed algorithm was compared with the standard algorithms like, Chinese remainder theorem, binary approach and squared multiplication approach. As the size of the exponent value increases, the proposed method shows better performance compared to other standard methods.