Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the target applications, these systems will also have custom memory and bus architectures. Because of performance and cost constraints, these systems must be carefully designed to balance system partitioning and resource sharing. The sheer size of the design space requires that tools be able to do this balancing. We have developed an augmented simulated annealing synthesis tool that uses system performance and layout evaluation to drive simultaneous data mapping, memory allocation and bus synthesis. Exploring these optimizations at the same time, our approach reverses traditional techniques and determines bus topology first rather than last, thereby exposing a larger design space and taking advantage of cost-saving resource sharing unavailable to previous approaches that allocate memories first. This results in 20% cost reduction for high-performance designs as well as 27% for low-cost designs in comparison with an approach that performs memory allocation and data mapping separately from bus synthesis.

Flash memory is being actively employed in a variety of embedded systems such as digital cameras, MP3 players, cell phones, solid state disks (SSDs), and digital media broadcasting (DMB) devices. This paper considers performance issues in file systems that employ Flash memory as a storage medium. Firstly, it explores the characteristics of Flash memory and identifies the cost of block cleaning as the key performance bottleneck for Flash memory analogous to the seek time in disk storage. Then, it defines three performance parameters, namely, utilization, invalidity, and uniformity and derives a formula for block cleaning cost based on these parameters. It is shown that, of these parameters, uniformity exerts the strongest influence on the cost of cleaning and that uniformity is a file system controllable parameter. Finally, we design a uniformity-aware page allocation scheme and analyze how enhanced uniformity affects the block cleaning cost with various workloads. Real implementation experiments conducted on an embedded system show that the scheme proposed here typically reduces the cleaning time by 20 to 30% compared to the traditional sequential allocation scheme that is used in YAFFS.

In this paper, we propose techniques for fast cycle-approximate multi-processor SoC simulation with timed transaction level models and OS models. Cycle-approximate simulation with an abstract model is widely used for fast validation of a multi-processor SoC in early design stages. However, the performance gain of abstract-level simulation is limited by the overhead of synchronizing multiple concurrent processor/module simulators, which is inevitable in timed simulation. To reduce the synchronization overhead, we adopt the synchronization time-point prediction method, which consists of two phases: static code analysis and dynamic scheduling of synchronizations. In the static analysis phase before simulation, it estimates minimum execution time from every point in the code to the nearest synchronization point. Then, during simulation, it pessimistically predicts the synchronization time-points based on the estimates. The proposed approach targets fast cycle-approximate simulation of a system with delay annotated SW code and transaction level models of HW with dynamic behavior. We present, in this paper, techniques to analyze such abstract models of SW and HW and schedule minimal number synchronizations during cycle-approximate simulation of the models. Experiments show that the approach achieves orders of magnitude higher performance in cycle-approximate multi-processor SoC simulation.

The hardware/software co-exploration is a critical phase for a broad range of embedded platforms based on the System-On-Chip approach. Traditionally, the compilation and the architectural design sub-spaces have been explored independently. Only recently, some approaches have analyzed the problem of the concurrent exploration of the compilation/architecture sub-spaces. This paper proposes a framework to support the co-exploration phase of the design space composed of architectural parameters and source program transformations. The objective space is multi-dimensional, including conflicting objectives such as energy and delay. In the proposed framework, heuristic co-exploration techniques based on Pareto Simulated Annealing (PSA) have been used to efficiently explore the architecture/compiler co-design space. A first result of this paper consists of showing how the architecture/compiler co-exploration can be more effective than a traditional two-phase exploration. Since the co-exploration space is quite large, to speed up the co-exploration phase by several orders of magnitude over simulation-based approaches, a methodology based on analytical models has been introduced in the co-exploration framework. The goal of analytical models is to quickly evaluate energy/delay metrics at the systems level, while maintaining accuracy with respect to simulation-based co-exploration. The proposed co-exploration framework has been applied to a parameterized SoC superscalar architecture during the execution of a selected set of multimedia applications.

This paper[3.5pc] presents the Platform Designer (PD) framework, a set of SystemC based tools that provide support for modeling, simulation and analysis of multiprocessor SoC platforms (MPSoC), at different abstraction levels. PD provides mechanisms for interconnection specification, process synchronization and communication, thus allowing the modeling of a complete platform, in a unified environment. To do that it uses an extension of the ArchC ADL and acsys, a tool that enables the automatic generation of a SystemC simulator of the platform. The main advantages of this approach are twofold. First, designers have more flexibility since they can integrate and configure different processors to the platform, using a single environment. Second, it enables a faster design space exploration, given that it automatically generates SystemC simulators of whole platforms at distinct abstraction levels. A number of platform variations can be tried out with minor design changes, thus reducing design time. Experimental results show the suitability of the platform simulator for design space exploration. Real applications (with medium complexity) run in the platform in few minutes. Combined with the facility to generate platforms with minor changes, this feature allows an improvement of the design space exploration.

We describe a toolbox for the analysis of Systems-on-a-chip written in SystemC at the transaction level. The tool is able to extract information from SystemC code, and to build a set of parallel automata that capture the semantics of a SystemC design, including the transaction-level specific constructs. As far as we know, this provides the first executable formal semantics of SystemC. Being implemented as a traditional compiler front-end, it is able to deal with general SystemC designs. The intermediate representation is now connected to existing formal verification tools via appropriate encodings. The toolbox is open and other tools will be used in the future.

In this paper, we propose a methodology for accelerating application segments by partitioning them between reconfigurable hardware blocks of different granularity. Critical parts are speeded-up on the coarse-grain reconfigurable hardware for meeting the timing requirements of application code mapped on the reconfigurable logic. The reconfigurable processing units are embedded in a generic hybrid system architecture which can model a large number of existing heterogeneous reconfigurable platforms. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by our developed high-performance data-path. The methodology mainly consists of three stages; the analysis, the mapping of the application parts onto fine and coarse-grain reconfigurable hardware, and the partitioning engine. A prototype software framework realizes the partitioning flow. In this work, the methodology is validated using five real-life applications. Analytical partitioning experiments show that the speedup relative to the all-FPGA mapping solution ranges from 1.5 to 4.0, while the specified timing constraints are satisfied for all the applications.

We describe a method of polynomial simulation to calculate switching activities in a general-delay logic circuit. This method is a generalization of the exact signal probability evaluation method due to Parker and McCluskey, which has been extended to handle temporal correlation and arbitrary transport delays. The method can target both combinational and sequential circuits. Our method is parameterized by a single parameter l, which determines the speed-accuracy tradeoff. l indicates the depth in terms of logic levels over which spatial signal correlation is taken into account. This is done by only taking into account reconvergent paths whose length is at most l. The rationale is that ignoring spatial correlation for signals that reconverge after many levels of logic introduces negligible error. When l = L, where L is the total number of levels of logic in the circuit, the method will produce the exact switching activity under a zero delay model, taking into account all internal correlation. We present results that show that the error in the switching activity and power estimates is very small even for small values of l. In fact, for most of the examples, power estimates with l = 0 are within 5% of the exact. However, this error can be higher than 20% for some examples. More robust estimates are obtained with l = 2, providing a good compromise between speed and accuracy.

The International Technology Roadmap for Semiconductors [3] predicts chip complexities by the end of this decade silicon of around 1 billion transistors integrated on a single piece of silicon. It will open new frontiers in terms of applications in areas/devices ranging from security systems (e.g. video surveillance), control systems (e.g. automotive control), individual health systems (e.g. hearing aids) to main stream consumer products in such areas as personal communication (e.g. cell phones), personal computing (e.g. PDA), entertainment (e.g. MP3 players), video/photo (e.g. digital still/video cameras) and many more. It can be observed that especially the latter group of main stream consumer products is subject to severe competition between major manufacturers and thus leading to two effects from a consumer’s point of view:

Validation of an System-on-Chip (SoC) design with networking capability needs global simulation of the whole system including the network as well as the SoC design itself. Especially, it is needed to validate the interoperability of SoCs from different vendors. In this paper, we propose a simulation environment and simulation techniques for efficient validation of such SoC designs and apply them to networked Bluetooth SoC designs. The environment enables two types of simulation. One is modular enough to include the simulation of other vendors' Bluetooth devices and the other is optimized to achieve fast simulation in developing in-house Bluetooth devices. Especially, the former is scalable in that it keeps the constant simulation runtime despite the increase of the number of Bluetooth devices. Since multiple simulators are involved, the global simulation is still slow. Thus, the simulation efforts need to be minimized to shorten the design cycle. We present two simulation techniques, a concept called grouped message for reduction in simulation runtime and a system debug scenario called fix---modify---restart for reduction in the number of simulation runs. The former is to reduce inter-process communication overhead between simulators in the global simulation. The latter is to reduce repeated simulation runs in the conventional design cycle. Experimental results show the scalability of the presented simulation environment, reduction in simulation efforts by two simulation techniques.