- Research Article
- 10.1088/2631-8695/ae6d7f
FPGA-Based Fault Injection and TMR Evaluation for Program Counter Reliability in the LEON3 Processor
- May 13, 2026
- Engineering Research Express
- Afef Kchaou + 2 more +2
Abstract This work presents an experimental analysis of single-event upset (SEU) vulnerability in the program counter (PC) of the LEON3 soft-core processor and evaluates triple modular redundancy (TMR) as a hardware-level mitigation strategy. Using FPGA-based emulation with the NETFI+ fault injection framework, SEUs are injected into the 30 most significant bits of the PC across all active pipeline stages. Results reveal that vulnerability is highly stage-dependent: the Fetch (FE) and Decode (DE) stages exhibit 100% sensitivity, as any bit-flip immediately disrupts control flow, while later stages (RA, EX, ME) are fully masked due to natural overwriting of PC values. The Exception (XC) stage shows only marginal sensitivity (0.02%). To address this localized fragility, TMR is applied to the entire integer unit (IU), triplicating pipeline logic. Under single-replica SEU injection, TMR achieves 0% sensitivity, fully masking all faults. Even in pessimistic multi-replica fault scenarios, where two or all three replicas are simultaneously corrupted, the system demonstrates strong resilience, reducing observable error sensitivity by up to 10× compared to the unprotected baseline. Resource overhead includes a 56% increase in LUTs and 28% in registers on a Xilinx Virtex-5 FPGA. These results confirm that the PC is the dominant source of SEU-induced control-flow failure in LEON3 and that TMR provides complete protection in realistic singlefault conditions while maintaining robustness under rare multi-fault events. The study establishes TMR as a highly effective countermeasure for LEON3-based systems operating in radiation-prone aerospace and space environments.
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