The IBM Z processor continues to improve over previous System Z processors, but for the first time it does so without a technology improvement as the baseline enabler. The IBM z15 was designed in the same 14-nm High-Performance GLOBALFOUNDRIES technology as the IBM z14 and yet still added 20% more cores, doubled the L3 cache, and increased the L2 cache by a third while also adding a third peripheral component interconnect express (PCIe) port to the chip and an elliptic curve cryptography engine into each core. This article discusses the design, tool, and methodology enhancements required to increase the design content so significantly while maintaining the chip size and power limits from the previous z14 design. This article also discusses other design and methodology improvements that were made possible via the deeper understanding of the technology and how to more fully leverage it in a second generation.

The IBM z15 supports the new IBM Z Hardware Management Appliance optional feature, which provides redundant Hardware Management Consoles (HMCs) and Support Elements (SEs) that run on redundant physical servers inside the CPC (Central Processor Complex) frame. This eliminates the need for having to manage one or more separate physical servers for HMCs outside of the frame. This article describes the host HMC/KVM (kernel-based virtual machine) and Virtual SE environment, which is completely managed by IBM Z firmware as a true appliance. It also illustrates the firmware integrity monitoring environment for the host HMC/KVM extended to the Virtual SE to provide secure boot protection for firmware and continuous monitoring and the utilization of a shared trusted platform module. It describes how physical system errors are processed by problem analysis firmware running on the Virtual SE, thereby enabling online guided repair instructions running on the Virtual SE to be used for both HMC and SE detected errors. This article will shares the innovative design basics of the IBM Z Hardware Management Appliance feature, which has significant positive impact potential for both clients and IBM.

With the growth of IBM Z and LinuxONE in the cloud, customers are expecting their workloads and data to have the same levels of security, isolation, and privacy as running on-premise. In order to achieve these levels of trust, the IBM z15 and LinuxONE III provide the IBM Secure Execution for Linux facility, which isolates customers’ data from each other, as well as from the cloud administrators. Unlike other solutions in the industry, IBM Secure Execution does not require remote attestation, thus simplifying the deployment of applications into the protected environment. Also, unlike some other solutions in the industry, the integrity of data is protected end-to-end, that is, from the boot image on disk to memory as it is paged by the hypervisor and throughout execution. The isolation and integrity are provided by hardware and trusted firmware known as the ultravisor. In this article, we describe the security model of IBM Secure Execution, the functionality of the hardware and ultravisor, as well as the required changes to the hypervisor in order to support protected virtual machines.

The introduction of heterogeneous computing via GPUs from the Sierra architecture represented a significant shift in direction for computational science at Lawrence Livermore National Laboratory (LLNL), and therefore required significant preparation. Over the last five years, the Sierra Center of Excellence (CoE) has brought employees with specific expertise from IBM and NVIDIA together with LLNL in a concentrated effort to prepare applications, system software, and tools for the Sierra supercomputer. This article shares the process we applied for the CoE and documents lessons learned during the collaboration, with the hope that others will be able to learn from both our success and intermediate setbacks. We describe what we have found to work for the management of such a collaboration and best practices for algorithms and source code, system configuration and software stack, tools, and application performance.

The fi eld of artifi cial intelligence (AI) has grown tremendously in recent years with the advent of Deep Neural Networks (DNNs) that surpass humans in a variety of cognitive tasks. It is estimated that the digital universe is growing at a rate of approximately 60% per year. This abundance of data, coupled with exponential gains in compute power, has enabled remarkable computational tools that have improved our understanding of today's incredibly complex economies and societies. Moreover, it has ushered in a new era of computing: the cognitive, or AI, era, in which data is considered a new natural resource and AI algorithms are indispensable tools. This special issue of the IBM Journal of Research and Development builds a bridge from conventional distributed learning systems, to hardware solutions that minimize data movement from the compute to memory, to novel hardware approaches on the horizon for deep learning for both training and inference. We have a collection of ten contributions from leading authorities in their fi elds that summarize the state of the art and show original research results.

In this article, we present innovative microarchitectural designs for multilayer deep neural networks (DNNs) implemented in crossbar arrays of analog memories. Data is transferred in a fully parallel manner between arrays without explicit analog-to-digital converters. Design ideas including source follower-based readout, array segmentation, and transmit-by-duration are adopted to improve the circuit efficiency. The execution energy and throughput, for both DNN training and inference, are analyzed quantitatively using circuit simulations of a full CMOS design in the 90-nm technology node. We find that our current design could achieve up to 12–14 TOPs/s/W energy efficiency for training, while a projected scaled design could achieve up to 250 TOPs/s/W. Key challenges in realizing analog AI systems are discussed.

Many modern and emerging applications must process increasingly large volumes of data. Unfortunately, prevalent computing paradigms are not designed to efficiently handle such large-scale data: The energy and performance costs to move this data between the memory subsystem and the CPU now dominate the total costs of computation. This forces system architects and designers to fundamentally rethink how to design computers. Processing-in-memory (PIM) is a computing paradigm that avoids most data movement costs by bringing computation to the data. New opportunities in modern memory systems are enabling architectures that can perform varying degrees of processing inside the memory subsystem. However, many practical system-level issues must be tackled to construct PIM architectures, including enabling workloads and programmers to easily take advantage of PIM. This article examines three key domains of work toward the practical construction and widespread adoption of PIM architectures. First, we describe our work on systematically identifying opportunities for PIM in real applications and quantify potential gains for popular emerging applications (e.g., machine learning, data analytics, genome analysis). Second, we aim to solve several key issues in programming these applications for PIM architectures. Third, we describe challenges that remain for the widespread adoption of PIM.