The analog layout design for the RF front-end circuits has remained a critical and time-intensive stage within the integrated circuit development cycle. Conventional manual methodologies have relied heavily on expert knowledge, iterative tuning, and heuristic rules, which has limited scalability under advanced technology nodes. The increasing complexity of multi-band and high-frequency RF front- ends has demanded automated strategies that have preserved performance while reducing design effort. Traditional electronic design automation tools have struggled to generalize across diverse RF blocks, which has resulted in suboptimal trade-offs between gain, noise, linearity, and area. Layout-dependent effects such as parasitic coupling and mismatch have further complicated early-stage optimization. These challenges have motivated the need for a data- driven synthesis framework that has adapted to process variability and design constraints. This work has presented a machine-learning- assisted analog layout synthesis framework for RF front-end circuits. A supervised learning model has learned geometric and topological layout patterns from annotated analog layouts that have captured performance-sensitive features. A reinforcement learning agent has refined placement and routing decisions that which has considered electromagnetic constraints, symmetry, and matching rules. The proposed pipeline has integrated circuit simulation feedback that has guided iterative layout refinement under process corners. Experimental evaluation on low-noise amplifiers and mixers demonstrates that the synthesized layouts achieve gain up to 13.4 dB, noise figure as low as 1.4 dB, linearity of -17.0 dBm, layout area of 1165 µm², and parasitic capacitance of 20 fF, outperforming existing template-based, optimization-driven, and reinforcement learning placement methods. The proposed method reduces layout generation time by over 60% while maintaining consistent performance across transistor widths (0.16–0.24 µm) and lengths (0.32–0.36 µm), indicating strong generalization and suitability for next-generation RF front-end designs.

The implementation of 2D DWT is a challenge using CMOS technology for miniature device (65nm minimum). For applications like biomedical engineering the area and power consumption are to be reduced. The Limitation of Existing methods is addressed in this paper and an alternate method of implementing the algorithm is presented. In addition, problems lie on high critical path due to the presence of multipliers, Delay is high due to critical path and computation, Execution Speed is less due to multipliers in existing DWT architecture. On the other hand below 45nm the problems in CMOS devices on leakage current, limitations on threshold voltage, short channel effect, high field effects and dopant number fluctuations, and interconnect delays are faced. The work focuses on designing the 2D DWT architecture using FinFETs which has leakage power superiority and power minimization. The proposed VLSI architecture for lifting based 2D-Discrete wavelet transforms (DWTs) using FinFET in 32nm technology is efficient when compared to the existing convolution- based architecture. The Predict and update stage of lifting based DWT without multiplier is implemented using HSPICE. The critical delay due to multiplier usage is eliminated. The multiplier less design enhances the performance of the system.

Partial discharge (PD) is a localized dielectric breakdown in high- voltage insulation systems that can lead to catastrophic equipment failure if undetected. Early and accurate detection of PD is critical in ensuring the reliability and longevity of high-voltage equipment such as transformers, GIS (Gas Insulated Switchgear), and cables. Traditional sensors and narrowband antenna systems have limited sensitivity and frequency range, making them less effective for detecting weak PD signals over wide spectra. The narrow operational bandwidth and low sensitivity of conventional PD detection systems impede accurate localization and characterization of PD phenomena, especially under noisy or variable frequency conditions. There is a pressing need for a robust detection mechanism that combines broad frequency response with high detection sensitivity. This study proposes a Broadband Antenna System specifically designed for PD signal acquisition. The system incorporates a log-periodic dipole array (LPDA) antenna integrated with a low-noise amplifier (LNA), coupled to a high-speed digitizer. The LPDA provides ultra-wideband coverage from 50 MHz to 1.5 GHz, enabling the capture of various PD signatures. Finite Element Method (FEM)-based simulations in CST Microwave Studio validate the antenna design. Real-time testing is performed in a controlled high-voltage laboratory environment using a 100 kV test transformer and calibrated PD sources. The proposed antenna system demonstrated a 25% improvement in sensitivity and a 40% increase in detection range compared to standard narrowband antennas. It accurately detected PD pulses with charge magnitudes as low as 5 pC under noisy environments.

Backscatter communication has emerged as a key enabling technology for ultra-low-power and batteryless wireless platforms, especially in the context of the Internet of Things (IoT) and pervasive sensing systems. Traditional designs often treat the antenna and RF circuitry independently, leading to suboptimal performance due to impedance mismatches, low energy harvesting efficiency, and poor communication reliability. Flexible materials and novel antenna structures have gained attention for wearable, implantable, and conformal applications but face challenges in maintaining performance consistency under mechanical deformation. This paper proposes a co-design methodology for flexible RF/antenna systems to optimize energy harvesting and communication efficiency in wirelessly powered backscatter communication platforms. The method integrates the antenna and RF front-end design to ensure impedance matching, maximize power transfer, and enable flexible operation. A meandered dipole antenna integrated with a Schottky-diode-based rectifier is designed using flexible polyimide substrate. The design ensures mechanical flexibility while achieving high RF-DC conversion efficiency. Simulations using CST Microwave Studio and co-simulation with Keysight ADS validate the antenna-rectifier co-design. Experimental results show up to 52% RF-DC conversion efficiency at 915 MHz under +5 dBm input power. Backscatter communication using On-Off Keying (OOK) achieves a range of 6 meters with minimal bit error rate under ambient powering conditions. The co-design improves energy harvesting by 19.4% and communication range by 27% compared to non-co-designed setups.

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Modern CMOS processors face a significant challenge in power consumption, primarily due to switching and leakage power. With rising demands for energy-efficient systems, especially in mobile and IoT devices, managing dynamic and static power has become essential. Conventional clock gating techniques lack adaptability to workload variability, leading to inefficient power savings. Fixed gating schemes either over-constrain performance or underperform in power savings. This work proposes a Low-Power Reconfigurable Match Table (RMT)- based Clock Controller that dynamically adjusts clock gating granularity based on real-time workload profiling. The system leverages a match table reconfiguration mechanism, enabling fine- grained control of clock signals to idle submodules. Implemented in a 45nm CMOS processor simulation environment, this approach combines workload prediction and table-driven reconfiguration for minimal leakage and switching overhead. Simulation results show a 38.6% reduction in switching power and a 29.3% reduction in leakage power compared to traditional fixed clock gating, with only 1.2% performance overhead. Power savings remain consistent across varied computational loads.

Precision agriculture increasingly depends on real-time monitoring and automation to enhance crop yield and reduce resource waste. Traditional irrigation systems either overuse or underutilize water due to lack of real-time sensing and decision-making, leading to poor water resource management. This research proposes a real-time embedded system using a NodeMCU ESP8266 microcontroller integrated with DHT11 (humidity and temperature), soil moisture sensors, and a solenoid valve to implement smart irrigation. The algorithm evaluates sensor data to trigger irrigation only when soil moisture falls below a defined threshold. Simulations in the Proteus environment and real-time tests demonstrated a 38.5% water savings and a 24.2% increase in yield efficiency compared to traditional systems. The proposed system also outperformed existing fuzzy logic and timer-based irrigation systems in energy efficiency and response time.

Microstrip circuits form the backbone of modern high-frequency communication systems, offering compact and efficient solutions for signal processing and transmission. However, the design of these circuits is challenging due to the intricate interplay of electromagnetic (EM) parameters, material properties, and circuit dimensions. Traditional EM simulation methods, while accurate, are computationally intensive and time-consuming, limiting their applicability for rapid prototyping and optimization. To address these challenges, this study integrates deep learning techniques with electromagnetic simulations to enhance microstrip circuit design efficiency. A Recurrent Neural Network (RNN)-based framework is proposed to predict the frequency-dependent behavior of microstrip circuits, leveraging temporal data from iterative EM simulations. The RNN model is trained on a diverse dataset of simulated circuit configurations, capturing the relationships between physical parameters, design constraints, and performance metrics. The proposed approach significantly reduces computational overhead by approximating the results of full-wave EM simulations while maintaining high accuracy. Validation against benchmark EM simulation tools shows that the RNN model achieves over 95% prediction accuracy with a 70% reduction in simulation time. Additionally, this framework enables real-time optimization of circuit designs, accelerating the iterative design process without compromising performance.

Thin and thick film materials are widely used in modern electronic circuits due to their ability to provide miniaturization, high performance, and cost-effective production. Thin film technology involves depositing layers of conductive, resistive, and dielectric materials onto a substrate, typically using methods like vacuum deposition or sputtering. Thick film technology, on the other hand, uses a screen-printing process to deposit paste-like materials onto substrates and is known for its durability and adaptability to harsh environments. Both technologies play crucial roles in designing analog and digital circuits, especially in fields like telecommunications, automotive electronics, and medical devices. The increasing demand for smaller, faster, and more efficient electronic devices has put pressure on the development of high-performance circuits using thin and thick film technologies. A key challenge is optimizing material properties to balance electrical performance, thermal management, and mechanical reliability in both analog and digital circuits. This study explores the design and performance evaluation of analog and digital circuits using thin and thick film materials. Thin film circuits were fabricated using sputtering techniques to deposit layers of resistive and conductive materials with precise thickness control. Thick film circuits were created by screen-printing conductive, resistive, and dielectric pastes onto ceramic substrates. Electrical performance was tested for both types of circuits, focusing on parameters such as resistance, capacitance, and inductance. The thin film circuits demonstrated superior electrical performance with lower parasitic inductance and capacitance, achieving a resistance tolerance of ±1% and a thermal coefficient of resistance (TCR) of ±50 ppm/°C. The thick film circuits, while having slightly higher parasitic values, offered robustness and mechanical stability in high-temperature environments, with TCR values ranging from ±100 to ±250 ppm/°C. Both technologies showed significant promise, with the choice of material depending on the specific application requirements for analog and digital systems.

In the rapidly evolving landscape of modern electronics, memory devices and circuits play a pivotal role in determining system performance, energy efficiency, and scalability. Traditional memory technologies, such as Dynamic Random Access Memory (DRAM) and NAND flash, face challenges related to scaling limits, latency, power consumption, and endurance, particularly as demands for faster and more efficient data storage grow. Emerging non-volatile memory (NVM) technologies like Resistive Random Access Memory (ReRAM), Phase-Change Memory (PCM), and Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) offer potential solutions to these challenges, but their combination into existing systems poses design and manufacturing hurdles. The primary problem lies in balancing storage performance with power efficiency while ensuring scalability for advanced applications such as artificial intelligence (AI), Internet of Things (IoT), and high-performance computing (HPC). Innovations in circuit design, including advanced error-correction mechanisms, adaptive voltage scaling, and low-power architectures, are critical in enhancing the overall performance of memory systems. This study employs a hybrid approach, combining novel circuit design techniques with the combination of emerging NVM technologies. Simulations were performed to evaluate the performance metrics, including write latency, energy consumption, and endurance. Results show that ReRAM-based memory designs achieved a 35% reduction in write latency and a 50% improvement in energy efficiency compared to traditional DRAM, while PCM demonstrated superior endurance with up to 10^8 write cycles. Furthermore, STT-MRAM circuits showed promise with a 40% reduction in standby power consumption. These advancements in memory circuits and devices highlight the potential for significant improvements in storage performance and efficiency, addressing the growing needs of modern electronic systems and paving the way for future innovations in computing.