ACS fed directional monopole suitable for high data rate communication with simple and compact structure, high gain and heavy bandwidth is presented. Antenna’s bandwidth ranging from 3.8 to 10.29 GHz, with uniformly oriented directional radiation pattern and polarization make it suitable for high data rate communication applications such as ISM5.2 and ISM5.8 WLANs, HIPERLAN2 and HiSWANa. It also covers 95% of FCC specified UWB band too. The peak gain of the antenna is obtained as 7.84 dBi with efficiency greater than 88 %. Electrical equivalent circuit modeling of the antenna is also developed and the results obtained are discussed.

In recent years, the integration of Micro-Electro-Mechanical Systems (MEMS) into sensor networks has shown promising potential for advancing circuit theory applications. This research addresses the increasing demand for efficient and high-performance implementations by proposing a novel methodology utilizing Field-Programmable Gate Arrays (FPGA). As circuit theory applications continue to evolve, there is a pressing need for innovative solutions that can handle the intricate demands of modern electronic systems. MEMS sensor networks offer advantages in terms of miniaturization, low power consumption, and enhanced sensing capabilities. However, existing implementations face challenges in achieving real-time processing and scalability, prompting the exploration of FPGA-based solutions. Current implementations of MEMS sensor networks for circuit theory applications often encounter bottlenecks related to processing speed and resource utilization. The research gap lies in the lack of efficient methodologies that can harness the parallel processing capabilities of FPGAs to address these challenges, ensuring real-time data processing and optimal resource allocation. The proposed methodology involves the design and implementation of an FPGA-based architecture specifically tailored for MEMS sensor networks. Leveraging the parallel processing capabilities of FPGAs, the architecture aims to enhance real-time data processing, reduce latency, and provide scalability for diverse circuit theory applications. The integration of FPGA with MEMS sensor networks is expected to result in a versatile platform capable of handling complex tasks efficiently. The results demonstrate significant improvements in processing speed and resource utilization compared to traditional implementations. The FPGA-based MEMS sensor network architecture exhibits enhanced performance in real-time circuit theory applications.

In real-time image processing, the demand for efficient solutions has surged with the proliferation of applications spanning from autonomous vehicles to medical diagnostics. This study addresses the imperative need for accelerated machine learning algorithms to enhance the processing speed of image-related tasks. The research focuses on leveraging Field-Programmable Gate Arrays (FPGAs) to implement hardware acceleration, exploiting their parallel computing capabilities. The advent of machine learning in image processing has revolutionized various industries, yet real-time applications encounter computational bottlenecks. This research delves into hardware acceleration using FPGAs to overcome these constraints, offering a novel approach to expedite machine learning algorithms. Traditional software implementations of machine learning algorithms often fall short in meeting real-time processing requirements. This research aims to bridge this gap by exploring FPGA-based hardware acceleration, addressing the performance limitations hindering the seamless integration of machine learning into real-time image processing systems. While existing literature acknowledges the potential of FPGA-based acceleration, a comprehensive exploration of its application for real-time image processing is lacking. This research fills the void by presenting a detailed method and empirical results, contributing to the limited body of knowledge on FPGA-accelerated machine learning in the of image processing. The study employs a systematic approach, integrating machine learning algorithms onto FPGAs through hardware description languages. The implementation is optimized to exploit parallelism inherent in FPGAs, resulting in a tailored hardware solution for real-time image processing. Comparative analyses against software implementations provide insights into the performance gains achieved. The experimental results demonstrate a significant enhancement in processing speed, validating the efficacy of FPGA-based hardware acceleration for machine learning algorithms in real-time image processing applications.

Fractional Open-Circuit Voltage (FOCV) - Maximum Power Point Tracking (MPPT) technology is a novel approach for optimizing energy harvesting in low-powered systems operating at 220 GHz, a challenging frequency range. This paper introduces FOCV as an efficient MPPT technique, utilizing fractional voltage measurements to determine the optimal operating point for energy extraction in 220 GHz multi solid-state circuits. By employing FOCV, the proposed energy harvesting system achieves enhanced power efficiency, making it suitable for applications with strict power constraints. Additionally, this paper addresses the electromagnetic interference (EMI) challenges associated with operating at such high frequencies, presenting mitigation strategies to ensure reliable and interference-free operation of the FOCV-based energy harvesting system in the 220 GHz multi solid-state circuits. The results demonstrate the effectiveness of the FOCV - MPPT technology in improving energy harvesting efficiency while minimizing EMI-induced performance degradation.

In recent years, quantum cell automata (QCA) has emerged as a promising optimization technique for real-time embedded systems design. QCA leverages quantum computing principles to perform parallel and coherent computations, enabling efficient exploration of vast solution spaces. This paper explores the application of QCA in the hardware-software co-design of real-time embedded systems, aiming to achieve enhanced performance, reduced power consumption, and improved reliability. The study investigates the partitioning of tasks between hardware and software, the design of hardware accelerators, and the development of efficient algorithms for real-time constraints. Furthermore, the paper addresses the optimization of communication interfaces to facilitate seamless interaction between hardware and software components. The results demonstrate the potential of QCA in revolutionizing the design and optimization of real-time embedded systems through its ability to exploit quantum parallelism and coherence.

Digital Filter Optimization (DFO) is one of the features that manages limiting the expansion of optical fiber transmission networks to exceedingly high speeds, large capacities, and great distances. DFO requires a great amount of computational effort, and this paper presents a novel optimisation technique that is based on the DFO approach. The optimisation approach that has been described has the potential to significantly cut down on the required quantity of mathematical effort that is essential for scenarios involving vast distances and enormous DFOs. When compared to the existing method that is the way that is most generally used, the proposed approach can reduce the complexity of the hardware implementation of commercial systems by more than 60%, and the optimisation impact is highlighted when the transmission distance is increased.

Quantum-dot cellular automata (QCA) is a promising technology for the construction of quantum circuits with or without memory. In this article, we propose that the matching unit of the content-addressable memory (CAM) cell be developed utilising a multi-layered XNOR gate that is based on electron interactions. The proposed QCA cell can reduce the required area by at least 15% and by as much as 92% when compared to the existing circuits. Furthermore, when the circuit is expanded to include QCA-CAM, it can improve performance by more than 15%. In addition, the cost-effectiveness of the cell as the size of the circuit increases is shown.

Implementation of optimal hybrid renewable energy technology is one of the most promising and environmentally beneficial ways to supplement the national grid energy supply to meet the energy needs of smart cities and rural areas. Renewable energy unpredictable growth is one of the system primary weaknesses, with a high initial cost, low reliability, and low total energy delivery technology, which can be remedied by using sufficient storage devices or by different interconnecting energy sources. An isolated hybrid energy system efficiency is improved using a genetic algorithm-based model developed in this research. The wind turbine, solar photovoltaics, diesel generator, and storage batteries are considered for data analysis and validation. The findings acquired using the standard program named HOMER are compared to the results obtained. The model input variables, energy costs, energy loss probabilities, and renewable portion are used to generate numerous factors such as sizing, number, and prices of various compounds, temperature, and autonomy days, as well as environmental considerations.

Generally, flash memory is a type of permanent memory for computers in which the contents can be reprocessed or erased electronically. Compared to programmable read-only memory that can erase electricity, operations on it can be performed on modules located in different locations. Flash memory is much less expensive than EEPROM, which is why it has become a dominant technology. Especially, in situations, this stable and long-term data retention is required. Its use is allowed in various cases like digital audio players, photo and video cameras, mobile phones and smartphones, and specialized Android applications on the memory card. Additionally, it is also used on USB flash drives, traditionally used to store and transfer information between computers. The proposed model provides enhancements to the storage capacity of various flash memory modules. In a saturation point, the proposed model achieved 93.03% of NOR Memory management, 89.31% of NAND Memory management, 94.25% of Ferroelectric RAM Memory management, and 94.53% of Magnetic RAM Memory management, 96.05% of Ovonic Unified Memory management and 96.16% of Salcogenide RAM Memory management.

Multi-gate MOSFETs have successfully enabled the extension of CMOS technology scaling in the nanoscale regime. Suppression of short channel effects (SCEs) and carrier transport enhancement are the two prime factors that matter the most for the improvements in digital CMOS technology. Multi-gate transport leads to suppression of SCEs and mobility improvement leads to carrier transport enhancement. Continuous scaling of device channel length in the nanoscale regime invites for the inclusion of scattering theory physics. The proposed work discusses the diverse carrier transport mechanisms occurring in Multi-gate MOSFETs in different channel length regimes. Further, a comparative analysis of carrier transport in long, short and ultra-short channel Multi-gate devices is done. The work also discusses the validity of the transport models and their scaling restrictions in different regimes. The simulation results demonstrate physical accuracy and continuity of the proposed models in the respective channel length regimes.