In floorplanning, our aim is to determine the relative locations of the blocks in the chip and the objective is to minimize the floorplan area, wirelength. Generally, there are so many strategies in VLSI floorplanning like area optimization, wirelength optimization, power optimization, temperature optimization and etc. This paper concentrates on area optimization. The goal of the physical design process is to design the VLSI chip with minimum area. The primary idea is to minimize the floorplan area by reshaping the blocks which are present inside the floorplan in order to attain the minimum area with less computational time. Proposed problem is redefined with an efficient meta-heuristic as Simulated Annealing algorithm which will provide optimal solution with less computation time. The proposed algorithm has been tested by using set of benchmarks of Microelectronics Centre of North Carolina (MCNC).The performance of the proposed algorithm is compared with other stochastic algorithms reported in the literature and is found to be efficient in producing floorplan with minimal area. The performance of the proposed algorithm seems to be better than the existing algorithms.

Over the years, semiconductor industry has undergone a rapid evolution which urges the SoCs to become communication-centric. For efficient on-chip communication, high performance routers are used. System on chip is an adaptable building design for the outline of center based Framework on-chip. A routing algorithm plays a dominant role in network’s operation. Several routing algorithms have been designed to cater several features and purposes. There are still a lot of requirements that has to be met. Such performance metrics are minimum latency, least power and maximum throughput. This paper deals with XY routing, PROM routing and DyAD routing. Performance is evaluated in terms of varying packet sizes and routing algorithms. The simulation results revealed a tradeoff between XY and PROM routing. In the measure of throughput and power, XY routing and DyAD routing scores on the top respectively. In case of non- uniform traffic loads, DyAD routing is well suited. This comparative study has been performed with the aid of NIRGAM NoC simulator in a 5 × 5 mesh based topology. Under wormhole switching, it is preferable to adopt DyAD routing in wireless routers in terms of low power and high throughput. This paper also forecast the need of adaptive implementation which must be application specific in the future years.

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