High-level Synthesis (HLS) generated IP designs are widely and effectively used in several image/video processing applications, consumer electronics applications as well as multimedia domains. However, several prior works have resolutely established major security vulnerabilities that HLS design process exposes. HLS framework/design flow can be maliciously exploited by an adversary/attacker. These vulnerabilities sanction malicious Trojan to be furtively injected during HLS design phases such as scheduling, mux-interconnect design stage, RTL datapath etc, resulting into compromised IP designs. This paper presents novel technique for detecting HLS hardware Trojans (HLS-HT) using random forest classifier based machine learning. The proposed detection framework is capable of detecting various types of state-of-the-art HLS-HT including performance degradation hardware Trojan (PD-HT), denial of service hardware Trojan (DoS-HT), battery exhaustion hardware Trojan (BE-HT), downgrade attack hardware Trojan (DA-HT), functional hardware Trojan (F-HT) and Time-bomb hardware Trojan (TB-HT). The proposed approach achieves high detection accuracy with zero false negatives for specific HLS-HTs considered here, ensuring sturdy IP design security.

Edge AI encompasses the technologies at the intersection of machine learning (ML) and embedded systems, enabling the development of intelligent applications on devices with minimal power consumption. These devices, although constrained by limited memory and computational resources, utilize sensors to interact with the physical environment and make decisions using ML algorithms. Edge AI thrives on the synergy between ML architectures and deployment platforms, as the design of one profoundly influences the efficiency and functionality of the other. This keynote paper delves into the rationale for employing microcontrollers and neural processing units (NPUs) designed for constrained use-cases as target platforms for Edge AI, explores the necessity of running ML locally, and highlights the opportunities and challenges these systems pose. It describes the main applications of Edge AI and provides references to a practical use case.

status: Published

Editor’s notes: This article presents a compact and efficient five-stage pipeline RISC-V microprocessor by incorporating architectural optimization techniques for IoT applications. —Hiroki Matsutani, Keio University, Japan