Metastability can arise whenever a signal is sampled close to a transition, leading to indecision as to its correct value. Synchronizer circuits, which guard against metastability, are becoming ubiquitous with the proliferation of timing domains on a chip. Despite the critical importance of reliable synchronization, this topic remains inadequately understood. This tutorial provides a glimpse into the theory and practice of this fascinating subject.

The one problem yet to be adequately solved in the growing asynchronous community is the synchronous design industry momentum, which has proven hard to redirect to include asynchronous options. This column examines some of the reasons why.

This theme issue brings to D&T readers important recent advances in functional verification of multicore SoC architectures using transaction-level models. Such a system-level approach is advocated to manage verification complexity and catch bugs early in the design cycle, so that the potential of multicore architectures can be realized for higher performance, power management, and functional diversity. Also in this issue are two features on testing and fault tolerance.

SRAMs capable of operating at extremely low supply voltages-for example, below the transistor threshold voltage-can enable ultra-low-power battery-operated systems by allowing the logic and memory to operate at the same optimal supply voltage. This review article presents SRAM techniques including new bit cells, novel sensing schemes, and read/write assist circuits for ultra-low-power applications.

This is a review of Electronic Design Automation: Synthesis, Verification and Test (Systems on Silicon) by Laung-Terng Wang, Yao-Wen Chang, and Kwang-Ting (Tim) Cheng, eds.

Timing-related defects are a major cause of test escapes and field returns for very deep-submicron (VDSM) integrated circuits. Small-delay variations induced by crosstalk, process variations, power supply noise, and resistive opens and shorts can cause timing failures in a design, leading to quality and reliability concerns. This article describes the authors' work with a previously proposed test-grading technique that uses output deviations for screening small-delay defects.