All Research Papers Published In IEEE Electron Device Letters

Research Article
10.1109/led.2026.3669828

IEEE Electron Device Letters Publication Information

Apr 01, 2026
IEEE Electron Device Letters

Research Article
10.1109/led.2026.3665044

High-Power Diamond Photoconductive Switch With Sub-Bandgap Responsivity

Apr 01, 2026
IEEE Electron Device Letters
Langning Wang + 4 more +4

In this study, a vertical diamond photoconductive semiconductor switch with sub-bandgap responsivity was developed. The device was fabricated on a 0.5 mm thick, nitrogen-doped diamond substrate. A sub-nanosecond laser pulse with a wavelength of 355 nm was used to axially trigger the device through a metal grid electrode. Under the 350-μJ 355-nm sub-ns laser pulse illumination and DC bias voltages of up to 20 kV (electric field: 20 kV/0.5mm=40 kV/mm), the device achieved sub-ns pulses with a peak current of 102 A, corresponding to a power capacity of 2 MW. The device Ron/Roff ratio is greater than 1011. This work highlights the potential of diamond in building ultrafast high-power photoelectric device.

Research Article
10.1109/led.2026.3659173

11.7 W/mm Continuous Wave Output Power in X-Band AlN-Buffer HEMTs

Apr 01, 2026
IEEE Electron Device Letters
Reet Chaudhuri + 6 more +6

Power amplifiers (PAs) using HEMTs with aluminum nitride (AlN) buffer layers promise superior thermal performance over the current generation of GaN-buffer HEMT PAs. However, the continuous-wave (CW) output power densities from AlN-buffer HEMTs have been limited to <6 W/mm so far. This work presents the advancement in the large-signal RF performance of AlN-buffer HEMTs with a 2× improvement in CW output powers. AlN-buffer HEMTs with 180 nm gate length and 2 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μm source-drain distance fabricated on 100 mm SiC substrates, show oncurrents of 1.1 A/mm and breakdown voltage ∼100 V. On-wafer load-pull power sweep measurements conducted at 10 GHz demonstrated a maximum CW power output (Pout) of 5.5 W/mm at 28 V and 11.7 W/mm at 50 V bias. At 50 V, the peak PAE of 49 % had an associated Pout 11.32 W/mm and linear gain of 9.35 dB. This significant power enhancement in AlN-buffer HEMT performance, coupled with its intrinsic thermal advantage over GaN-buffer HEMTs, paves the way for adoption in critical RF applications.

Research Article
10.1109/led.2026.3665632

Interlayer Co-Design Enabling a Large Memory Window and Robust Reliability in Ferroelectric Vertical Gate-All-Around FETs

Mar 04, 2026
IEEE Electron Device Letters
Runhao Han + 15 more +15

In this letter, we present an epi-Si channel ferroelectric vertical gate-all-around (FEVGAA) FET featuring a gate and channel interlayer (G.IL/C.IL) co-design to achieve a wide memory window (MW) and robust reliability. The performance enhancement stems from two synergistic mechanisms: (1) gate-injected charges (QtG) induced by the G.IL, and (2) C.IL nitridation, which raises trap formation energy while introducing positive fixed charges to improve endurance, retention, and read-disturb immunity. Enabled by this strategy, a record MW of 3.5 V is realized, representing a 7.7X expansion compared to the reference FE-only device. The maximum ISPE slope also improves 8.8X. Notably, the device endures 5×104 cycles with negligible Ion degradation at the large MW state. Endurance is further extended to 5×108 cycles with a nanosecond-level high operating speed. Moreover, the retention loss after 10 years is only 2.8%. In addition, the device exhibits strong immunity to read disturb for 106 cycles. This gate stack design expands the application of FEVGAA devices in high-density non-volatile memory.

Research Article
10.1109/led.2026.3659487

Improved Contact Properties in Violet Phosphorus via Bonding-Enabled Interfacing Engineering

Feb 03, 2026
IEEE Electron Device Letters
Shengxi Cai + 5 more +5

Violet phosphorus (VP) has emerged as a promising two-dimensional material for photodetectors due to its excellent electronic and optical properties. However, the high contact resistance and uncontrollable Schottky barrier height at the metal-semiconductor interface limit the performance of VP-based device. Here, supported by Hartree potential analysis, we propose a bonding-enabled interfacing engineering by introducing a 20 nm indium (In) buffer layer. VP nanoflakes were prepared via multi-step mechanical exfoliation. An atomically sharp interface and partial ln–P bonding was observed at the VP/In interface, which enhanced interfacial coupling and improve photocarrier collection efficiency. The VP/In/Au photodetector exhibits enhanced photoresponse compared to VP/Au devices. This work provides a viable interface engineering strategy for contact optimization in VP-based optoelectronic devices.

Research Article
10.1109/led.2026.3660264

A Simple and Efficient Multi-V th Tuning for FDSOI p-FETs by Cryogenic Floating Substrate

Feb 03, 2026
IEEE Electron Device Letters
Yi Han + 5 more +5

Cryogenic CMOS provides critical performance benefits for high-performance computing, space electronics, and quantum interfaces, including enhanced carrier mobility and steeper subthreshold swing (SS). However, cryogenic operation increases threshold voltage (Vth), necessitating higher supply voltages that offset these advantages. This work presents a novel Vth control strategy based on UTBB SOI technology, leveraging the cryogenic floating substrate (CFS) effect to enable nonvolatile Vth modulation. Compared to conventional back-gate voltage (Vback), the CFS approach demonstrates fourfold higher tuning efficiency while eliminating the need for additional control planes or process modifications. By combining CFS with Vback modulation, we achieve both wide-range Vth adjustment and precise fine-tuning. These advantages establish the CFS technique as a promising solution for ultra-low-power cryogenic CMOS applications.

Research Article
10.1109/led.2026.3652870

IEEE Electron Device Letters Information for Authors

Feb 01, 2026
IEEE Electron Device Letters

Research Article
10.1109/led.2025.3641532

New Low On-Resistance Lateral Superjunction With Strain-Induced Mobility Enhancement

Feb 01, 2026
IEEE Electron Device Letters
Mingzhe Li + 3 more +3

A novel Lateral Strained Superjunction (LSSJ) with low specific on-resistance (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ron,sp) is proposed and simulated in this letter. The partially relaxed Silicon-Germanium (Si1-xGex) layer, as the P-type pillars of LSSJ, induces biaxial tensile stress in the N-type Silicon (Si) pillars to enhance electron mobility. The Si1-xGex pillars across the drift region mitigates the lateral stress relaxation, enabling the high-voltage application of LSSJ. The charge compensation layer eliminates the substrate assisted depletion effect and modulates the surface electric field so as to improve the breakdown voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BV). A balanced superjunction structure with P-type Si1-xGex pillar and N-type Si pillar is achieved. The simulation results show that, for the lateral diffused metal-oxide-semiconductor (LDMOS) with a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BV above 400V, LSSJ exhibits a 20% reduction in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ron,sp and a slight 2% degradation in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BV compared to the SJ with a buried step doping (BSD) layer, thus resulting in a 18% improvement in figure-of-merit (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FOM). The LSSJ realizes a superior performance and is suitable for the LDMOS with a SJ drift region, especially for the next-generation narrow-pitch SJ, which faces the degradation in carrier mobility.

Research Article
10.1109/led.2025.3636677

Operation of AlGaN Channel HEMTs at 850 °C With ON/OFF Ratio >10 4

Feb 01, 2026
IEEE Electron Device Letters
James Spencer Lundh + 17 more +17

We report 850 °C operation of ultrawide bandgap (UWBG) Al-rich Al0.68Ga0.32N channel high electron mobility transistors (HEMTs) at atmospheric pressure in nitrogen ambient. Temperature dependent DC electrical characteristics were measured in situ up to 850 °C, after exposure to 850 °C for 60 minutes, and at 25 °C after high temperature testing. At 850 °C (time, t = 0 min), all HEMTs tested maintained an on/off ratio greater than 104 (maximum of 4.6×104). The threshold voltage demonstrated excellent stability with less than ±10% deviation. After returning to 25 °C, the devices showed negligible degradation. In fact, the off-state gate current decreased and on/off ratio slightly increased. The robustness of these UWBG AlGaN transistors at temperatures up to 850 °C demonstrates their viability for extreme environment applications.

Research Article
10.1109/led.2026.3653018

Atomic Layer Deposited Pd Nanoparticles in TiO 2 Thin Film Enabling Selective Photoresponse for Visual Nociceptor

Jan 29, 2026
IEEE Electron Device Letters
Song Sun + 4 more +4

The blue light spectrum (415–455 nm) penetrates the ocular media to the retina and causes damage to photoreceptor cells, however artificial visual nociceptors specifically responsive to harmful blue light are rarely reported. In this letter, an optoelectronic artificial synapse based on Pd nanoparticles (NPs) in-situ embedded in 20 nm-thick TiO₂ thin film was constructed via atomic layer deposition (ALD). Precise energy band matching enables efficient photo-generated carrier separation and directional transport under blue/green light, leading to enhanced wavelength-selective photoresponse for harmful blue light-responsive visual nociceptors. Furthermore, some key bio-synaptic functions could be also realized in this device with low electrical energy consumption of ~56 fJ per spike. ALD-derived optoelectronic synapse directly couples environmental stimulus perception and injury recognition, paving a competitive avenue for next-generation neuromorphic vision sensors and low-power wearable health-monitoring devices due to its scalable manufacturing capability.