This article presents a wide-input-range buck converter featuring a conduction-loss-minimized zero-voltage switching (ZVS) technique. The proposed ZVS topology enables accurate ZVS operation across a wide range of input voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {IN}}$</tex-math> </inline-formula>) and load current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {O}}$</tex-math> </inline-formula>). By keeping the auxiliary inductor current pulse in the ZVS branch separate from the main current paths, conduction loss is minimized, thereby enhancing efficiency across the entire load range. Furthermore, by reducing the voltage across the auxiliary inductor using an auxiliary capacitor, a small inductor is sufficient for ZVS. Furthermore, by implementing the ZVS control circuit directly in the high-voltage (HV) domain, propagation delays between HV and low-voltage (LV) domains are avoided, and thus, accurate ZVS operation is achieved. The converter was fabricated in a 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m BCD process with all power switches integrated on chip. Measurement results show that the converter achieves peak efficiencies of 91.7% and 92.5% at 42-to-5-V and 24-to-3.3-V conversion, respectively. Efficiency improvement is achieved across the entire 4-A load current range with just a 30-nH auxiliary inductor.

In this article, we propose a wideband mixer-first receiver with improved in-band (IB) linearity. It uses bootstrapped N-path mixer switches to achieve a constant <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state gate–source voltage for large IB signals. We analyze the tradeoff between <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state resistance and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small>-state subthreshold current in conventional mixer switches and introduce a method to break this tradeoff with the presented bootstrap technique. The mixer is followed by a degenerated LNTA featuring partial cancellation of its nonlinear output current. The receiver is fabricated in 22-nm FDSOI CMOS and achieves over 16-dBm IB IIP<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {_{3}}$</tex-math> </inline-formula> at room temperature and over 14-dBm IIP<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {_{3}}$</tex-math> </inline-formula> over the industrial temperature range. It has a 190-MHz I and Q baseband bandwidth, while its performance is demonstrated for a local oscillator frequency range from 1 to 8GHz.

A continuous beam angle resolution enables precise beam steering and prevents beam squinting, especially in dense environments where large arrays create narrow beams to maximize capacity. This work proposes a continuous beam angle reconfigurable four-element receiver (RX) for the FR3 frequency band. The implemented vector modulator (VM) phase-shifting mechanism is based on the slice-based RX for the coarse stage and phase-shifting polyphase filters (PPFs) in the local oscillator (LO) paths for the fine stage to overcome the limited phase resolution. The beamformer is equipped with current-mode true-time delay (TTD) units to further assist with better linearity performance and signal-to-noise ratio (SNR) improvement at the band edges. Fabricated in TSMC 65-nm complementary metal-oxide–semiconductor (CMOS), the prototype occupies an area of 1.65 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, consuming 14 mA/element centered at 7.5GHz. The measured maximum single-channel gain is 22 dB, with a minimum noise figure (NF) of 7.48 dB while having an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S_{11}\lt -10$</tex-math> </inline-formula>dB across 7.28–7.78-GHz input frequency span. A root mean square (rms) phase error of 0.76° is achieved while showing continuous phase shifting over 360°. The TTD units improve the beamformed down-converted 100-MHz wideband (WB) up to 1.5-dB gain at the band edge. Moreover, over-the-air (OTA) measurements show the reception of a single-tone signal at a 297.88-cm distance between RX and a horn antenna.

In situ timing monitoring significantly improves the energy efficiency of low-voltage digital ICs by eliminating the excessive timing margins inserted to address high PVT variations in conventional digital flows. However, such techniques face challenges related to design overhead and robustness. This article presents the early-monitoring error prediction (EMEP) technique to address these issues effectively. With minimal clock tree (CT) impact and low area (1.6%) and power overhead (2%), EMEP achieves 60% endpoint coverage. This wide coverage, combined with increased resilience against critical activity masking and variability, enhances system robustness. In addition, 4σ yield is ensured through statistical critical path identification. Automatically integrated into a 28-nm CMOS RISC-V microcontroller, EMEP recovers 86% of conventional energy margins and reduces energy consumption by 2.9 pJ/cycle (41%), outperforming traditional replicas by 61% and endpoint monitoring (EPM) techniques by 31%. EMEP operates the microcontroller with only 14.5% energy overhead compared with margin-free operation, which is essential to address activity uncertainty, becoming minimal when the slowest critical paths are active.

Clinical-ready neuromodulation devices for real-time monitoring and treatment of neurological disorders require a neural interface integrated circuit (IC) that supports therapeutic neurostimulation together with concurrent recording of neural activities from large brain regions. To address this need, this article presents an IC with 32 high dynamic range (HDR) electrocorticography (ECoG) recording channels and two programmable neurostimulators allowing bi-directional neural interfacing. The recording channel uses a 2nd-order continuous-time <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $</tex-math> </inline-formula> modulator (CTDSM) architecture with 12-tap finite impulse response digital-to-analog converter (FIRDAC) feedback facilitated by a pre-emptive current-steering excess loop delay (ELD) compensation scheme. By employing a high-performance linearized low-noise/low-power transconductance amplifier (L<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup>TA) in the input integration stage, the recording channel achieves 83-dB dynamic range (DR) with up to 222-mV<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> linear input range, and thus can accommodate large electrode dc offsets (EDOs) and stimulation artifacts. Thanks to the FIRDAC that relaxes component matching requirements, each recording channel occupies only 0.028 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.39~{\mu }$</tex-math> </inline-formula>W while being manufactured in standard 180-nm CMOS technology. The concurrent neural recording and stimulation capabilities of the chip have been validated in a mouse experiment in vivo, which shows that the recording channel can tolerate real stimulation artifacts and the recorded ECoG signals can be separated from the artifacts with high fidelity.

This article presents a hybrid voltage-time domain pipelined analog-to-digital converter (ADC). The proposed ADC employs a voltage-domain SAR quantizer for the coarse stage, while a time-domain quantizer is used for the fine stage. Ahybrid-domain dual-residue method is proposed to generate reference-embedded time-domain residues. It ensures full-scale matching between the converted time-domain residue and the time-domain reference of the fine stage. For the fine stage sub-quantizer, an interpolating time-to-digital converter (TDC) suited for dual-residue quantization is employed without using an external time-domain reference. A prototype ADC, implemented in a 40-nm CMOS process, occupies 0.034 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Operating at a sampling rate of 150 MS/s, the ADC achieves an SNDR of 61.1 dB and an SFDR of 75.5 dB at a Nyquist input, while consuming 2.54 mW, resulting in a Walden figure-of-merit (FoM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub>) of 18.3 fJ/conv.-step.