This article presents a 28-nm CMOS sub-terahertz (sub-THz) amplitude shift-keying (ASK) transceiver achieving competitive wireless and wireline communication performance. The over-the-air (OTA) link demonstrates 14 Gb/s/0.27 km, 16Gb/s/1m, and 27 Gb/s/12 cm without equalization (EQ), while supporting 64 Gb/s on-Off keying (OOK) and 40 Gb/s pulse amplitude modulation (PAM)4 in wireline mode. In the transmitter (TX), a power-boosting technique is proposed for the oscillator to maximize output power and DC-to-RF efficiency with a compact area. An ASK modulator incorporating analog-pre-distortion (APD) compensation is proposed to support high-efficiency and high-speed modulation. A compact 90–180 GHz power amplifier (PA) is utilized to deliver 15–18 dBm output power, with an integrated broadside balanced balun for differential signal interfacing. In the receiver (RX), a 110–160 GHz low-noise amplifier (LNA) with a switchable differential and single-ended interface is proposed, and a 90–180 GHz wideband envelope detector (ED) with DC-35 GHz baseband amplifier (BBA) is designed for high-speed demodulation. A novel metamaterial-loaded modified Vivaldi antenna and a wideband ground-signal-ground (GSG) pads to waveguide transition (WGT) are proposed for wireless link. The transceiver establishes new benchmarks for silicon-based sub-THz ASK systems, demonstrating the longest reported communication distance with competitive data rates, showcasing extensive communication applications.

Neuro-symbolic (NeSy) artificial intelligence (AI) integrates neural learning with symbolic reasoning to enable data-efficient, interpretable, and generalizable intelligence, making it a promising paradigm for human-like cognition. However, the heterogeneous and dynamic execution patterns of NeSy models pose fundamental challenges to conventional AI hardware, which is typically optimized for dense matrix operations. This article presents a fully programmable heterogeneous system-on-chip (SoC) fabricated in 40-nm CMOS, specifically designed to accelerate a wide range of NeSy workloads. The architecture features: 1) integrated resistive RAM (RRAM) and static random access memory (SRAM) neural-symbolic data paths; 2) ultra-dense (4.80 Mb/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>), energy-efficient (0.247 pJ/b) RRAM macros with edge-triggered and prolonged sensing; 3) scheduler-informed power management; and 4) programming support for variable resolution, vector lengths, and batching. The SoC supports multiple NeSy paradigms and achieves up to 10.8 TOPS/W energy efficiency and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.47\times $</tex-math> </inline-formula> power reduction across reasoning benchmarks. This work demonstrates the first end-to-end silicon system for generalizable and efficient NeSy inference.

This article presents a state-of-the-art design-agnostic clock, voltage, and electromagnetic pulse (EMP)-based fault-injection attack (FIA) detector. The efficient conversion of time-to-voltage information by integrating amplifiers transforms the time anomaly into the voltage domain, enabling its detection at a lower power consumption. The clock-glitch detector design consumes only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$53~\mu $</tex-math> </inline-formula>W of power, providing a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$33\times $</tex-math> </inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16\times $</tex-math> </inline-formula> improvement over prior art designs. In addition, the application-specific integrated circuit (ASIC) implementation of a dedicated voltage-based glitch detector consumes only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.27~\mu $</tex-math> </inline-formula>W. Variable threshold selection mechanisms are also deployed to address the changes for different process corners, supply voltages, temperature, and frequency of operation, ensuring comprehensive coverage under varying circumstances. Furthermore, this detector has demonstrated its capability to detect EMP-based glitch attacks on integrated circuits (ICs), marking a first-of-its-kind demonstration.

This article presents a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$64 {\times } 64$</tex-math> </inline-formula> SPAD flash LiDAR sensor that achieves a depth precision of 0.12% across a 70 m depth range. The sensor is built on a time-gated single-photon counting (TGSPC) architecture that integrates a back-side illuminated (BSI) single-photon avalanche diode (SPAD), a pulse-shaping circuit, a push-pull analog pulse counter, and column-parallel single-slope (SS) analog-to-digital converters (ADCs). A push-pull analog counter has been integrated into the pixel to significantly enhance the sensor’s ability to prevent saturation under high background light (BGL) conditions. Fabricated using a 110 nm BSI CMOS image sensor process, the sensor features a compact pixel pitch of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32~{\mu }$</tex-math> </inline-formula>m and a high fill factor of 33%. For 3-D depth sensing, it operates at 30 fps with a power consumption of 29.1 mW. It achieves a high photon detection probability (PDP) of 14.3% at 850 nm, enabling a depth precision of 8.4 cm at a depth range of 70 m, corresponding to the depth precision of 0.12%. These results are achieved through the use of a compact SPAD front-end circuit, a novel push-pull analog counter, and an optimized SPAD structure.

As emerging applications increasingly demand higher computational power from embedded memories, achieving sufficient performance and timing margins has become a significant challenge. This article introduces an algorithmically signed mask ROM, which incorporates a sign column into the original read-only memory (ROM) bitcell array to address the tradeoff between access speed and read margin. By generating optimized sign bits for the given data, the proportion of “1”-bits programmed in each column is constrained within a certain narrow range, effectively mitigating the tradeoff. SPICE simulations and silicon measurements of a 1.8-Mbit signed ROM implemented on 3-nm Fin-FET logic CMOS demonstrate read access time improvements of 12.7% and 13.8%, respectively. The proposed signed ROM, which is compatible with compiler implementation, has the potential to significantly enhance the performance of embedded memories, particularly for emerging high-performance applications.

This work presents a 3-in-1 multi-mode amplifier, including automatic gain control (AGC) and logarithmic gain, which achieves a total gain of 9.5–85.5 dB and an input-referred noise (IRN) of 4.7<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>Vrms within a bandwidth of 136 kHz. The PVT-focused amplifier design operates from −25 °C to 200 °C and does not require any trimming. Incorporating a parallel piecewise logarithmic approximation using nine passive-switched-capacitor (PSC) stages with a fixed gain of three (0.015 dB error per stage), the temperature stable absolute logarithmic error is 0.5 dB. This leads to a logarithmic conformity error (LCE) of 0.75 % up to 200 °C.

This article introduces an adhesive interposer-based reconfigurable multi-sensor patch interface with on-chip quantized time-domain feature extraction, tailored for heterogeneous physiological and environmental monitoring. A proposed patch concept includes integrated micro-scale structures for comfortable pressure-based reconfiguration, allowing easy attachment and detachment of various sensor elements. For embedding edge-computing capability into a miniaturized patch device with a conventional legacy microcontroller, its multi-sensor interface integrated circuit (IC) is proposed to include on-chip analog feature extraction and classification engines of quantized time-domain convolutional neural network (QTD-CNN) and one-shot computing binary neural network (BNN). The design employs 1-bit past-data quantization, analog normalization, and flexible time window schemes to minimize leakage problems in conventional analog engines and supports reconfigurable operations for healthcare and environmental applications. This interface IC includes five types of readout frontends for chemo-resistive sensors, electrochemical sensors, biopotentials, bioimpedance, and photoplethysmogram, where every path is designed to provide both wide dynamic range (DR) and compensation capability of gain and offset. A system-level prototype of the adhesive interposer-based reconfigurable patch interface has been developed, demonstrating its effectiveness in gas event and arrhythmia detection with hit rates of 91% and 92%, respectively.