An open-loop fractional output divider (FOD) with self-adaption frequency filtering for digital-to-time converter (DTC) gain and integrated non-linearity (INL) background calibration is presented in this article. The DTC is usually adopted in the FOD to compensate the quantization error. However, the delay of the DTC is sensitive to process, voltage, and temperature (PVT) variations, which necessities gain and INL calibrations. The existing FODs can only perform gain calibration or require prior knowledge to reduce spur level for a certain spur frequency. An FOD with self-adaption frequency filtering is proposed for DTC gain and INL background calibration. Spurious tones generated by the FOD are detected using a PLL-based self-adaption frequency filtering technique. The self-adaption frequency filtering quantifies the deviation of the FOD instantaneous output from its ideal output, which enables a zeroth/first/second-order DTC INL background calibration algorithm for reducing the spur level and jitter. In addition, a discrete-time model of the auxiliary PLL (aux-PLL)-based INL calibration loop is derived and analyzed. Fabricated in the 28-nm CMOS process, the proposed FOD occupies a core area of 0.084 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and covers an output range of 10–300 MHz. With a 100-MHz output frequency after the divide-by-2 divider, which corrects the output duty cycle to 50%, the FOD achieves spur level of less than -80 dBc both in the sub-integer-N (int-N) and the fractional-N mode. More than 41.9-dB spur reduction is achieved when enabling the calibration according to measurement results. The FOD achieves a 10-kHz–20-MHz integrated jitter of 310 fs rms.

This article presents a 32–38-GHz variable-gain phase shifter (VGPS) with a novel impedance-invariant vector modulation technique for highly precise phase and amplitude control. A negative-feedback magnetic-coupling (NFMC) method is proposed to stabilizes input and output impedances of variable gain amplifier (VGA), and it effectively alleviates the impedance variations at the different currents biased from the current digital to analog converter (DAC). The VGPS is fabricated with a 0.13-μm SiGe BiCMOS technology. It achieves a 7-bit phase resolution over 360<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup> and a 4-bit gain adjustment across a 7.5 dB dynamic range. The VGPS demonstrates exceptionally low rms phase and amplitude errors of 0.33<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>/0.10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup> dB in phase shifter mode and 0.23<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>/0.08<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup> dB in VGA mode at 35.5 GHz. The chip occupies a core area of 1062 × 534 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes only 7.4–12.2 mW dc power.

This article presents an 86.71875-GHz RF transceiver IC featuring a fully integrated clock and data recovery (CDR)-assisted carrier synchronization loop (CSL) for waveguide links. The carrier frequency of 86.71875 GHz is chosen to be the third harmonic of the baseband null frequency of 28.90625 GHz, and the carrier synchronization is achieved using a baseband CDR instead of power-and area-intensive RF circuits. The IC, fabricated in 28-nm CMOS, demonstrates 57.8125-Gb/s pulse-amplitude modulation-4 (PAM-4) data transmission over a 1.5-m waveguide channel while improving the timing margin by 38% compared to conventional methods. The Tx and Rx ICs occupying an area of 1.98 × 0.95 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> consume 190.1 and 117 mW at 57.8125 Gb/s, respectively. The test chip achieves the figure of merit (FoM) of 3.5 pJ/b/m in terms of throughput–distance and energy efficiency.

This work presents a digital phase-locked loop (PLL) incorporating an adaptive common-mode (CM) resonance tuning technique applied to a voltage-biased digitally-controlled oscillator (DCO). The method leverages the principle that the sensitivity of the oscillator frequency to a dither signal injected into the gate voltage of the cross-coupled transistors diminishes to near zero when the CM resonance is optimally tuned for minimal phase noise (PN). By detecting and nullifying this sensitivity, the proposed technique automatically adjusts the CM resonance to its ideal value. This background operation is continuous across the entire tuning range. The concept was validated through a digital PLL prototype fabricated in a 28-nm CMOS process, which achieved a jitter of 45.9 fs, a power-versus-jitter figure-of-merit of −257 dB, and a PN of −146.6 dBc/Hz at 10-MHz offset from a 4.75-GHz carrier, all within an active area of <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.21 mm² </b>.

This article introduces the industry’s first volume-production silicon-validated static random access memory (SRAM) designs fabricated using Intel’s 18A RibbonFET technology, incorporating PowerVia backside power delivery. The high-density 0.021-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SRAM cell achieves an array density of up to 38.1 Mb/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. With a high volume 34.3 Mb/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> macro implementation in silicon demonstrating improved minimum operation voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {MIN}}$</tex-math> </inline-formula>) with negative bitline (NBL) assist compared to similar designs on FinFET technology. Additionally, the high-current 6T SRAM high-current cell (HCC) exhibits improved <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {MIN}}$</tex-math> </inline-formula> without the need for assist techniques, in contrast to equivalent FinFET implementations that require both read and write assist mechanisms. The HCC macro demonstrates a frequency up to 5.6 GHz when operating at 1.05 V.

This article presents a single-link, dual-output wireless power transfer (WPT) system operating at 40.68 MHz for miniature, high-power biomedical implants. The elevated carrier frequency enables a millimeter-scale receiver (RX) coil while maintaining link efficiency and output power comparable to low-frequency WPT designs. End-to-end (E2E) efficiency is optimized through global power modulation using a dynamic <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small>-time (DOT) algorithm in conjunction with a fully integrated load-shift-keying (LSK) uplink. At the RX, a single-stage dual-output resonant-current-mode (DORCM) rectifier with single-mode zero-crossing-based control achieves zero-voltage switching (ZVS) and robust adaptability over varying coupling conditions. At the transmitter (TX), an adaptive-ZVS (AZVS) class-D power amplifier (PA) minimizes switching losses and electromagnetic interference (EMI). Both the TX and RX chips are fabricated in a 180-nm BCD process. Measurement results demonstrate dual-output voltage regulation at 1.2 and 2 V under DOT control (DOT Ctrl), with smooth switching behaviors observed at both the TX and RX. The DORCM RX supports seamless cold-start-up operation and achieves a peak power conversion efficiency (PCE) of 90.3% at 90.4-mW output power. The peak E2E efficiency is 51.2% at a coupling factor of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$</tex-math> </inline-formula> = 0.2. Enabling DOT modulation improves E2E efficiency by up to 18.2%, corresponding to a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.2{\times }$</tex-math> </inline-formula> reduction in TX input power. The system delivers up to 149.7-mW output power with a TX input voltage of 5 V.

In this article, we propose a new language model processor named the C-Transformer to address the external memory bottleneck of language models. It consists of three key functional blocks: 1) homogeneous deep-neural-network (DNN)–Transformer/spiking-Transformer core (HDSC) with a hybrid multiplication/accumulation unit (HMAU) to enhance hardware utilization; 2) output spike speculation unit (OSSU) to increase the energy efficiency of spike-domain processing; and 3) implicit weight generation unit (IWGU) with extended sign compression (ESC) to eliminate the external memory bottleneck. The chip is fabricated in Samsung’s 28-nm 1P8M CMOS technology and operates at a supply voltage of 0.7–1.1 V with a maximum frequency of 200 MHz and supports various tasks such as language modeling, translation, and summarization. For models like generative pre-trained transformer 2 (GPT-2), multilingual text-to-text transfer transformer (mT5), text-to-text transfer transformer (T5), and FairSeq MachineTranslation (FSMT), the C-Transformer achieves 0.21×–0.33× computation energy and 0.37×–0.41× external memory access (EMA) energy compared to the baseline. Our chip demonstrates 13.6% lower energy consumption than the previous state-of-the-art, despite having 2.1× more parameters. Moreover, it consumes 63.8% less energy with a similar parameter size. The C-Transformer can complete various language model tasks with <1 s latency, notably FSMT in 0.09 s and GPT-2 in 0.656 s. By combining DNN–Transformer and Spiking-Transformer architectures, the C-Transformer enhances computational energy efficiency, eliminates external memory bottlenecks, and enables language models such as GPT-2 to achieve state-of-the-art performance on mobile devices.

This article presents the design and implementation of a precision lock-in amplifier for universal capacitive sensing. While conventional capacitive transimpedance amplifier (C-TIA) based on lock-in detection can extract subtle capacitance changes from a noisy environment, the capacitance resolution is further limited by parasitic capacitance at the input node, the baseline capacitance of the sensor, and current noise introduced by input bias resistor. To address these limitations, this work proposes a zeptofarad (zF) resolution lock-in amplifier using three key techniques: 1) a self-calibrated negative capacitor (NC) to cancel the parasitic capacitance at C-TIA input; 2) baseline capacitance compensation to improve the dynamic range (DR), allowing the use of higher excitation voltages, thereby improving the SNR; and 3) multi-element pseudo-resistor (PR) to mitigate shot noise in the presence of elevated input dc current. The proposed lock-in amplifier was implemented in a standard 180-nm CMOS process, achieving a best-in-class resolution of 2.06 zF<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf {rms}}$ </tex-math></inline-formula> (BW = 10 Hz) while tolerating a maximum input dc current of 122 nA. This amplifier enables wideband lock-in detection from 1 kHz to 62 MHz. Both parasitic and baseline capacitance can be automatically calibrated in the foreground, considerably improving the speed and practicality of the measurement.

This article presents an always-half-inductor-current hybrid bidirectional converter (AHI-HBC) for USB-to-2-cell bidirectional power transfer. The converter achieves always-half-inductor current (AHI) in both directions compared to conventional bidirectional converters (CBCs) while using only 5-V transistors. This enables the elimination of high-voltage (HV) transistors, which have poor <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-resistance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{\mathrm { ON}}$</tex-math> </inline-formula>) performance and increase process costs. In addition, to address the challenge of varying charging current caused by changes in a battery voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm { BAT}}$</tex-math> </inline-formula>), we propose a normalized inductor current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N_{\mathrm { IL}}$</tex-math> </inline-formula>)-based adaptive target current controller that leverages the relationship between the inductor current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{L}$</tex-math> </inline-formula>) and output current to effectively regulate the battery charging current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm { BAT}}$</tex-math> </inline-formula>). By utilizing the proposed controller, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm { BAT}}$</tex-math> </inline-formula> adaptively tracks the target charging current regardless of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm { BAT}}$</tex-math> </inline-formula>, which varies depending on the state-of-charge. The prototype chip was fabricated in a 180-nm CMOS process with a 4.7-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>H inductor, two 10-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>F flying capacitors, and a 10-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>F output capacitor. With the greatest <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{L}$</tex-math> </inline-formula> reduction within the target USB-to-2-cell range, the converter demonstrated peak efficiencies of 97.4% (96%) in the forward mode and 97% (96.2%) in the on-the-go (OTG) mode with an inductor dc resistance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{\mathrm { DC}}$</tex-math> </inline-formula>) of 11.5 m<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $</tex-math> </inline-formula> (295 m<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $</tex-math> </inline-formula>).

This article presents the creation of a wireless, miniature implantable opto-electro neural interface device called NeuroFlare, capable of simultaneous neural recording and optical stimulation. NeuroFlare features a low-power, dual-modal application-specific integrated circuit (ASIC) fabricated using the 180-nm CMOS process. To support the power-intensive optical stimulation in NeuroFlare, the ASIC employs a novel linear-charging switched-capacitor stimulation (LC-SCS) structure. The LC-SCS, operating under only a 1.2-V supply voltage, can illuminate the LED with a driving voltage three times the supply voltage and large current pulses of up to 12 mA while maintaining a high charging efficiency of 86.4%. In addition, LC -SCS requires only one off-chip capacitor, greatly facilitating device miniaturization. To accurately record neural signals in the presence of stimulation artifacts, the ASIC employs a delta-sigma modulator (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M)-based recording front end with a wide dynamic range (DR) to directly digitize the neural signals. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M features a 2nd-order loop architecture implemented using a linearized transconductance-capacitor (Gm-C) integrator followed by an active noise-shaping (NS) successive approximation register (SAR) quantizer. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M with a power consumption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9.8~{\mu }$ </tex-math></inline-formula>W provides a peak DR of 83.7 dB, corresponding to a 400-mVPP linear input range. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M’s 173.8-dB figure of merit (FoMDR) indicates its superior energy efficiency. The ASIC is assembled into a prototype of NeuroFlare measuring <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.8 \,\, {\times } \,\, 3.5 \,\, {\times } \,\, 0.7$ </tex-math></inline-formula> mm3. The recorded light-evoked local field potential (LFP) verified the functionality of NeuroFlare in vivo.