Targeting implantable medical devices (IMDs), we presented a simultaneous wireless power and data transfer (WPDT) system, using the fundamental and harmonic components of the bridge inverter on the transmitter (TX) side to, respectively, deliver power and forward data. On the receiver (RX) side, we discovered the data-flipping problem using the conventional full-bridge rectifier (FBR), which is ascribed to the interference from its distorted input voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} {_{\text {AC}}}$ </tex-math></inline-formula>). This problem is solved by the proposed interference-free rectifier (IFR) featuring its low-distortion staircase <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} {_{\text {ac}}}$ </tex-math></inline-formula>. To further alleviate the crosstalk between power and data transfer, a tapped coil three-capacitor (TL3C) topology on the TX side together with a resonant topology on the RX side was proposed. The IFR IC was fabricated by a 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m CMOS process, with which a 6.78-MHz WPDT system was implemented. Experimental results showed that compared with the conventional FBR, the interference voltage ratio (IVR) in the proposed IFR was reduced from −17 to −45.2 dB. At a distance of 6 mm, our system supported simultaneous 54.4-mW load power (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P} {_{\text {Load}}}$ </tex-math></inline-formula>) and 4.0-Mb/s forward data rate (DR) with 48.6% end-to-end efficiency (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\eta _{\text {E2E}}$ </tex-math></inline-formula>). Both figure of merits (FoMs) for power and data transfer are the highest compared with previous results.

Analog compute in memory (CIM) with multilevel cell (MLC) resistive random access memory (ReRAM) promises highly dense and efficient compute support for machine learning and scientific computing. This article introduces analog to digital converter (ADC)-assisted bit-serial processing for efficient, high-throughput compute. Bit-serial digital to analog converters (DACs) and 8-bit binary-weighted multicycle sampling (BWMCS) ADCs perform analog vector-matrix multiplication (VMM) on MLC-based crossbar arrays. A direct drive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g}_{m}$ </tex-math></inline-formula>-boosted transimpedance amplifier (TIA) enables high-speed crossbar readout. We present a system on chip (SoC) prototype consisting of four self-contained ReRAM-based CIM macros and a reduced instruction set computer-five (RISC-V) host. The test chip is fabricated in 65 nm CMOS with foundry-integrated MLC ReRAM. We trained LeNet1 for handwritten digit classification and mapped the CNN weights differentially to 3-bit MLC ReRAM across multiple CIM macros. The classification accuracy loss is 1.6% when compared to the quantization-aware trained model. The measured raw and normalized peak efficiencies are 20.7 and 662 TOPS/W, respectively. The compute density is 8.4 TOPS/mm2.

This work proposes a static random access memory (SRAM)-based delta-sigma computing-in-memory (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> CIM) processor for edge intelligence applications in 22-nm CMOS technology. This <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> CIM processor effectively mitigates redundant operations associated with unchanged input features and adaptively adjusts computing-in-memory (CIM) outputs to achieve a near-zero-mean (NZM) distribution, thereby benefiting the energy-intensive analog-to-digital converters (ADCs). The proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> CIM macro involves three main innovations at the architecture and circuit levels: first, it replaces absolute inputs with deltas computed from consecutive input values, resulting in a notable 35.8% reduction in energy consumption for the CIM array; second, the delta matrix-vector multiplications (MVMs) implemented by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> CIM array can self-adaptively shift the analog CIM outputs to be NZM distributed, facilitating streamlined centralized data processing; and third, the introduction of a least significant bit first (LSB-first) ADC, whose number of conversions adjust dynamically based on instantaneous input values, allows for efficient analog output conversion of highly concentrated NZM analog data without compromising full-scale range or precision. Compared with state-of-the-art (SOTA) analog SRAM-based CIM macros, this work achieves superior area-energy efficiency product by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.25{\times }$ </tex-math></inline-formula> with up to 21.38 TOPS/W and 1.44 TOPS/mm2 at full precision of 8b input, 8b weight, and 24b output, through bit-serial inputs and shifter-and-adder.

As emerging applications raise ever-boosting and varying computational demand, the reconfigurable accelerator is becoming prevalent due to balanced performance, efficiency, and flexibility. Although the functions of its processing elements (PEs) and interconnections can be defined by a high-level software program, the circuit parameters are mostly managed by hardware or the compiler, leaving opportunities for in-depth optimization and novel features. Considering that the circuit adjustment is of great value in terms of low power and security, this article presents a novel software-defined accelerator named cross-domain software-defined chip (CDSDC), of which most chip properties including circuit parameters, logic, and pipelines can be programmed synergistically by software at runtime. With this design scheme, CDSDC provides new features including: 1) dynamic pipeline-voltage-frequency scaling (DPVFS), which combines pipeline reconfiguration with voltage-frequency scaling to generate an optimal chip configuration for various applications; 2) intrinsic physical unclonable function (PUF), which leverages the uniform PEs as measured circuit delay elements by adjusting the circuit parameters, extracting the entropy of manufacturing process variation, and taking response bits as a PUF; and 3) device-binding confidential configuration, which uses the intrinsic PUF and ASCON algorithm to encrypt/decrypt configuration. The CDSDC has been implemented in silicon as a 28-nm Taiwan Semiconductor Manufacturing Company (TSMC) HPC+ 1P8M 6-mm2 test chip, operating at peak 400 MHz and 0.9 V, achieving a peak energy efficiency of 51 GOPS/W. It improves performance and efficiency for cross-domain patterns of computation by DPVFS. It improves hardware security against reverse engineering attacks by using intrinsic PUF and device-specific encrypted configuration flow.

A fully integrated, non-frequency-translating, low-impedance transceiver (TRX) front end for cellular base stations (BSs) covering 1.25–5.5 GHz is presented. The transmitter (TX) features two variable gain feedback pre-power amplifier (PPA) stages, a power amplifier (PA), and an RF notch filter based on frequency translation for suppressing spurious signals. The receiver (RX) features a low noise amplifier (LNA), a variable gain amplifier (VGA), and an equalizer supporting three concurrent frequency bands with orthogonal frequency and gain tuning. The PA and LNA use a 12.5-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> differential impedance, primarily to boost PA output power and bandwidth (BW). Special emphasis is put on the thermal analysis of the PA and the techniques to improve the cooling. When operating with full PA supply (7.4 V), including antenna-switch and package losses, the TX reaches a record saturated output power (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {sat}}$ </tex-math></inline-formula>) of 38.1 dBm at 3.4 GHz, and for a 100-MHz 16-QAM orthogonal frequency-division multiplexing (OFDM) signal at 2.7 GHz, the TX delivers an output power of 32.6 dBm with an error vector magnitude (EVM) of -17.6 dB, with a complete TX efficiency of 13.5%. With a reduced PA supply of 3.8 V, an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${8} {\times } {100}$ </tex-math></inline-formula> MHz 256-QAM OFDM signal with 21.6 dBm was measured with EVM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\lt } {-}31.1$ </tex-math></inline-formula> dB. The TX filter achieves about 40-dB notch depth at 1–6-GHz notch frequencies, and the 20- and 30-dB rejection BW can be controlled from 1 to 10 MHz and from 0.4 to 4 MHz, respectively. The front end has an RX noise figure (NF) of 1.3–2 dB, while the third-order intercept point (IIP3) is above -12.4 dBm, at maximum gain (29 dB) over the frequency range of 1.55–4.8 GHz. The passive equalizer improves the RX interference handling and is analyzed using closed-form expressions. The active part of the die, manufactured in 22-nm fully depleted silicon on insulator (FD-SOI) CMOS technology, occupies 6.6 mm2.

This article presents a compact 13-bit 2-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) designed to enhance energy efficiency under various comparator input common-mode voltage scenarios. The proposed comparator structure features a complementary split pre-amplifier to extend the input common-mode range, resulting in an SNDR drop of approximately 1 dB even at a near 0-V ADC input common-mode voltage of 0.038 V. Furthermore, the proposed grounded-finger capacitive digital-to-analog converter (CDAC) reduces the impact of hard-to-scale fringe capacitance with a regular structure in order to reduce the number of CDAC elements and area. Utilizing these techniques, the prototype SAR ADC implemented in a 65-nm CMOS LP process achieves an uncalibrated integral non-linearity (INL) of 1.07 LSB, an 87.4% reduction in elements, and 70.6-dB SNDR in a 0.0372 mm2, consuming only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15.1~{\mu }$ </tex-math></inline-formula> W at 0.75 V that results in a Walden figure of merit (FoMW) of 2.72 fJ/conversion-step.

This article presents a 112-Gb/s/pin single-ended four-level pulse-amplitude modulation (PAM-4) crosstalk cancellation (XTC) transceiver (TRX) designed to support data rates of up to 224 Gb/s through a pair of differential channels. The receiver (RX) employs a mismatch-mitigation single-ended-to-differential (S2D) converter for minimizing pseudo-differential mismatch. A four-tap feed-forward equalizer (FFE) using a multi-phase clock (MPC) technique is proposed to compensate for pre- and post-cursor inter-symbol interference (ISI) noise with low power consumption. The transmitter (TX) reconfigurable XTC technique is adopted to cancel mild crosstalk noise flexibly, while the multiple-input-multiple-output (MIMO)-XTC technique in the RX is used to eliminate severe inductive crosstalk noise robustly. Fabricated in 28-nm CMOS, the TRX achieves a bit error rate (BER) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\lt } 10{^{-10}}$ </tex-math></inline-formula> at 112-Gb/s PAM-4 transmission with a channel loss of 31 dB at the Nyquist frequency and an energy efficiency of 2.77 pJ/b.

This article presents a 7-GHz fractional-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> digital phase-locked loop (DPLL) without any digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter (DTC) or dither. Utilizing a cascaded fractional divider, the fractional spur offset frequency can be shifted beyond the PLL bandwidth, resulting in less fractional spur degradation at near-integer channels. A pseudo-differential DTC (PD-DTC) technique that can cancel the even-symmetric nonlinearity components is also employed to achieve a better suppression of the fractional spur. Thanks to the aforementioned two techniques, a −62.1-dBc worst-case fractional spur can be achieved without degrading the in-band PLL phase noise (PN) or PLL locking time. Occupying 0.23-mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area in a 65-nm CMOS process, this PLL can achieve a 143.7-fs integrated jitter with a 100-MHz reference frequency and 8.89-mW power consumption, which translates to a figure-of-merit (FoM) of −247.4 dB.

This article presents a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1920{\times } 1080$ </tex-math></inline-formula> array 2-D/3-D image sensor with 3-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> s row-time single-slope ADC (SSADC) and 100-MHz demodulated locked-in pixel. To obtain reliable depth information, a backside-illuminated <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6{\times } 6~{\mu }$ </tex-math></inline-formula> m pinned photodiode (PPD) pixel with high built-in electric field is used to accelerate charge transfer. Storage diodes (SDs) are designed to collect demodulated electrons for correlated double sampling (CDS) readout. The two-tap pixel and differential multiplexing readout architecture realize both image modes (2-D and 3-D) working with full-HD resolution. To overcome the limitation of quantization speed in conventional structures, we introduce a 4-bit time-to-digital converter (TDC) into the 8-bit SSADC for residual information quantization, achieving 3-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> s row-time and 12-bit readout accuracy. In addition, we have proposed a detection and correction circuit in the data stitching process, which resolves error code problem. The common-mode output of two different taps is removed through full differential readout for the background light (BGL) canceling. A prototype chip is fabricated in a 110-nm backside illumination CMOS image sensor (BSI CIS) process. The designed PPD enabled a low depth noise of under 0.43% over the range of 0.3–1.5 m, with a modulation frequency of 100 MHz. By adopting the high-speed SSADC, the 2-D and 3-D frame rates achieve 300 and 60 frames/s, respectively.