This paper presents an improved particle swarm optimization (PSO) method and applies it to the design of a hybrid asymmetric load modulated balanced amplifier (H-ALMBA) with high linearity. A description is provided of the H-ALMBA topology as well as the improved PSO method with individually self-adaptive hyperparameters (Improved PSO-ISH). The design process as well as the optimization procedure are described in detail. In addition to output power and efficiency, linearity performance, including AM/AM and AM/PM characteristics, is also considered during optimization. The performance of H-ALMBA optimized by the proposed method is presented and compared to the initial design, the ADS built-in optimizer, and other methods of PSO that are currently available. Due to the introduction of Latin hypercube sampling (LHS) and a secondary optimization step in the improved PSO-ISH method, the optimization performance has been greatly enhanced. According to the measured results, the H-ALMBA designed using the proposed method achieves a saturation drain efficiency (DE) between 59.5% and 64.8%, and a DE of 45.7%-58.1% in the 10dB output back-off state (OBO), with an output power of 41.5 dBm-44.2 dBm from 1.8GHz to 2.6GHz. The variation range of AM/AM is less than 4.1dB and that of AM/PM is less than 11.5°, demonstrating high linearity. Additionally, modulated signal tests are conducted. A 20-MHz 5G new radio (NR) signal with 10-dB peak-to-average power ratios (PAPRs) is used. A high level of linearity is achieved without the use of digital predistortion (DPD).

This work presents a SAR ADC architecture designed for single-ended-to-differential conversion with low-energy switching and area efficiency. By incorporating top and bottom sampling techniques, the architecture achieves seamless conversion without the need for extra DAC hardware. It offers configurable fully-differential or single-ended modes by means of Vcm-based switching. With 75% reduced total capacitance compared to the conventional method, consistent energy savings are achieved across configurations. Implemented in 130nm CMOS, this design features an array of 48 ADCs and custom on-chip voltage references integrated within the SparkPix-S ASIC, a device tailored for X-ray imagers. With a nominal sampling rate of 5 MSps and 1.2V supply voltage, the achieved SNDR is 54.5dB, with +0.98/-0.86 LSB of DNL and +0.83/-1.26 LSB of INL. The core SAR ADC average power consumption is 96μW, resulting in a FOM of 40.1 fj/conv-step, all within a compact active area of 0.0212mm2.

A comprehensive nonlinear analysis of autonomous and periodically forced fully-differential, negative-resistor LC oscillators is presented. Through nonlinear transformations in the state space, it is shown that oscillators within this class exhibit qualitatively similar dynamical behavior in terms of their limit cycles and bifurcation curves, at least within an open region containing the origin. The case of autonomous, complementary BJT oscillators is used to validate the qualitative analysis and demonstrate a general approach of how to numerically extend the bifurcation curves away from the equilibrium point and determine the oscillatory conditions. When external periodic force is present, we focus on the special case of periodically multiplicatively-forced fully-differential, negative-resistor, LC oscillators and use Harmonic Balance techniques to derive analytical expressions estimating the locking range in the weak injection regime. The results are used to calculate the locking range of a harmonically forced complementary BJT oscillator yielding explicit expressions closely aligned with experimental measurements, thus verifying the validity of the analysis.

Deploying deep neural networks (DNNs) on resource-constrained IoT devices remains a challenging problem, often requiring hardware modifications tailored to individual AI models. Existing accelerator-generation tools, such as AMD’s FINN, do not adequately address extreme resource limitations faced by IoT endpoints operating in bare-metal environments without an operating system (OS). To overcome these constraints, we propose MARVEL–an automated, end-to-end framework that generates custom RISC-V ISA extensions tailored to specific DNN model classes, with a primary focus on convolutional neural networks (CNNs). The proposed method profiles high-level DNN representations in Python and generates an ISA-extended RISC-V core with associated compiler tools for efficient deployment. The flow leverages (1) Apache TVM for translating high-level Python-based DNN models into optimized C code, (2) Synopsys ASIP Designer for identifying compute-intensive kernels, modeling, and generating a custom RISC-V and (3) Xilinx Vivado for FPGA implementation. Beyond a model-class specific RISC-V, our approach produces an optimized bare-metal C implementation, eliminating the need for an OS or extensive software dependencies. Unlike conventional deployment pipelines relying on TensorFlow/PyTorch runtimes, our solution enables seamless execution in highly resource-constrained environments. We evaluated the flow on popular DNN models such as LeNet-5*, MobileNetV1, ResNet50, VGG16, MobileNetV2 and DenseNet121 using the Synopsys trv32p3 RISC-V core as a baseline. Results show a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> speedup in inference and upto <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> reduction in energy per inference at a 28.23% area overhead when implemented on an AMD Zynq UltraScale+ ZCU104 FPGA platform.

Emerging nonvolatile memory technologies offer promising avenues for novel computing approaches. Among them, resistive random access memories (RRAMs) stand out due to their nonvolatility, fast switching speed, compact size, and low power consumption. Logic techniques such as complementary resistive switch (CRS) and memristor ratioed logic (MRL) are prominent non-stateful logic techniques. CRS is well-suited for crossbar arrays, mitigating sneak-path currents, while MRL integrates effectively with CMOS logic, enabling the construction of complete logic circuits using CMOS inverters. Both techniques share a common trait: their logical output is read/defined under a high input voltage. However, the nonlinear I-V characteristics of RRAM devices reduce the resistance ratio, limiting reliable logic operation. This paper experimentally demonstrates CRS and MRL gates using HfO2 memristors within a crossbar array. We show that the voltage-dependent resistance degradation of the high-resistance state (HRS) significantly reduces the resistance ratio during logic evaluation, impairing output reliability and cascading potential. Simulation results confirm these nonlinear effects. To address these challenges, we introduce a two-phase read scheme for CRS and a pre-initialization strategy for MRL that sets both devices to HRS before operation. These methods improve current spike detectability and enhance output voltage levels, respectively. The proposed solutions advance the feasibility of robust in-memory logic with nonlinear memristive devices.

Incremental Delta-Sigma (I-DS) analog-to-digital converters (ADCs) are widely utilized in applications requiring high-resolution Nyquist conversion. Accurate performance prediction of these converters is crucial for efficient design and optimization. Existing state of the art (SoA) equations are either lacking sufficient accuracy or simplicity in predicting quantization noise performance under various architectural scenarios. This paper reviews the derivation and limitations of existing performance prediction models. A more general and accurate analysis is derived for predicting the performance of I-DS ADCs, addressing the shortcomings of the conventional approaches. The validity of the proposed performance prediction is rigorously evaluated through extensive simulations across a broad range of architectural choices. The results establish the new model as a robust tool for predicting the performance of I-DS ADCs, advancing the SoA, and facilitating more effective design strategies in the field.

This work introduces a rigorous time-domain approach for studying the complex synchronization dynamics of periodically forced electronic oscillators, based on the well-developed theories of Phase-Amplitude reduction via the Koopman operator and dynamics of circle maps. The paper is structured in two parts. Part I presents the theoretical foundation and the numerical application of the theory. Under suitable forcing, the reduced equations simplify to a one-dimensional phase model—represented by a circle map—whose bifurcations are determined by the Phase Response Curves. This map efficiently captures the oscillator’s dynamics and enables accurate computation of resonance regions in the forcing parameter space. The influence of global isochron geometry on the map validates their critical role in phase locking, extending previous results in the theory of electronic oscillators. For more general forcing scenarios, the full Phase-Amplitude reduction effectively describes the synchronization dynamics. The developed time-domain approach demonstrates that the same limit cycle oscillator can produce periodic output with tunable spectral characteristics, operating as a frequency divider, or function as a chaotic or quasiperiodic signal generator, depending on the driving signal. As an illustrative example, the synchronization dynamics of differential LC oscillators is studied in detail. Part II is dedicated to confirming the validity, generality, and robustness of the introduced approach, which is first presented as a detailed step-by-step methodology, suitable for direct application to any oscillator. The Colpitts and ring oscillators are analyzed theoretically, and their resonance diagrams are numerically computed, following the approach established in Part I. Simulations of realistically implemented models in the Cadence IC Suite show that both synchronized and chaotic/quasiperiodic states are accurately predicted by the reduced circle map. Notably, despite the use of simplified analytical models, the theoretical framework effectively captures the qualitative behavior observed in simulation. The consistency between the theoretical and simulation results confirms both the robustness and general applicability of the proposed approach.

This paper presents a bandgap voltage reference (BGR) circuit with a wide supply voltage and temperature range, suitable for automotive applications. We use multi-objective artificial intelligence (AI) optimization to improve both the temperature coefficient (TC) and line regulation simultaneously ensuring VREF accuracy over a wide temperature and supply voltage range. The design uses a lateral double-diffused MOS (LDMOS) transistor to handle high-voltage stress. To extend the operating temperature range, we use low-power quasi-beta compensation. A regulated-cascode current mirror minimizes errors from current replication, enhancing the TC. Fabricated in 180nm BCD, results from 10-chip measurements show an average TC of 44.9 ppm/°C at a 2.0V supply, within the range of -40°C to 150°C. Line regulation measures 0.13 mV/V or 0.0144%/V from 2V to 12V across the entire temperature range.

Grid type energy storage has inertia support capability, and unbalanced grid voltage will cause grid type energy storage current fluctuation and active power fluctuation. In this paper, a control method for unbalanced current in grid type energy storage based on negative sequence virtual impedance is proposed, analyze the reasons for the fluctuation of grid type energy storage current, and adopts the inner-loop positive-negative sequence separation control method, adding virtual impedance to suppress the negative sequence current only in the negative sequence control loop. And the relationship between the virtual impedance values and system stability in the background of grid harmonics are analyzed. Finally, simulations and experiments show that the addition of virtual impedance only in negative sequence does not affect the normal operating conditions, but has the characteristic of producing effects under unbalanced grid voltage. The method is simple to implement and the output current and active power fluctuations of the grid type energy storage are effectively suppressed.