Advances in integrated circuit (IC) technology have amplified the effects of process, voltage, and temperature (PVT) variations, particularly dynamic IR drop, which severely affects timing. Post-silicon IR drop monitoring circuits are lacking, forcing designers to reserve substantial static guard bands for worst-case scenarios, compromising energy efficiency. Inspired by biomimetics, this paper proposes an Actiniaria-shaped structure for distributed monitoring of multiple IR drop hotspots without invading critical paths (CPs). It comprises “lightweight tentacles + central monitor”. The tentacles use voltage-sensitive cells to sense the impact of IR drop on timing, while also supporting adaptive tuning for global variations. By using on-chip PVT sensors, Actiniaria tracks the timing characteristics of the longest CP in real time under PVT variations. A two-stage pre-warning timing monitor captures timing margins and employs adaptive voltage/frequency scaling (AVFS) strategies to compress redundant guard bands. When applied to an open-source multi-core RISC-V processor fabricated in 22-nm CMOS, Actiniaria achieves a 40.6% reduction in power consumption through non-invasive dynamic IR drop monitoring while having only 0.08% area overhead.

A fully-integrated galvanic isolator for gate drivers that supports high-speed, asynchronous, full-duplex communication is presented. Data transmission from the microcontroller to the power device is achieved using amplitude-shift keying (ASK) at 100 Mb/s, while simultaneous communication in the opposite direction is implemented using frequency-shift keying (FSK) at 167 Mb/s. A delay-locked loop (DLL)-based FSK demodulator enables robust operation in a completely asynchronous communication scenario. Prototypes were fabricated in a 0.13 μm HV CMOS technology, covering an area of 2.2 mm. The system operates from a low 1.5 V supply with a total power consumption of 8.2 mW. Measured propagation delays are under 8 ns for ASK and below 4 ns for FSK at their respective maximum data rates.

This paper presents a fully digital true random number generator (TRNG) and noise generator (NG) based on a chaos system. We design the chaos random number generator (CRNG) using the proposed Euler-based modified Lorenz system with periodic perturbation and modified modulo unit. The chaos NG (CNG) processor integrates the CRNG with Box-Muller modules to produce Gaussian noise signals. This paper also analyzes the impact of step size on the infinite divergence phenomenon and performs the NIST test to ensure CRNG’s mathematical stability and reliability. The chip was designed and fabricated using TSMC 40 nm CMOS technology. The proposed CRNG chip achieves a throughput of 24.86 Gbps at a maximum clock frequency of 259 MHz, with a core power consumption of 17.82 mW and an energy efficiency of 0.717 pJ/bit. This performance achieves the highest throughput among state-of-the-art ASIC-based TRNGs. Additionally, the proposed processor achieves a throughput of 1.53 Gsamples/s with a clock frequency of 255 MHz, a core power consumption of 62.73 mW, and an energy efficiency of 41 pJ/sample. This performance achieves the highest throughput and the best energy efficiency in state-of-the-art works.

This paper introduces the design of a 4-phase quadrature clock generator (QCG) featuring digital automatic calibration. The QCG architecture comprises a duty cycle correction (DCC) circuit, a digitally controlled delay line (DCDL), and an open-loop quadrature error correction (QEC) circuit utilizing phase interpolators (PI). The DCDL generates clock signals with an initial coarse quadrature phase error, which is subsequently refined by the QEC to achieve a phase error of less than 10. A finite state machine (FSM) conducts background calibration for the DCC and DCDL coarse correction, employing a pattern-detecting strategy to disable calibration, thereby eliminating spurious tones and deterministic jitter from the output clocks. Measurement results demonstrate that the proposed QCG achieves a phase error below 0.8∘ across a frequency range of 5 to 10 GHz, with an integrated jitter of 61.1 fs and a power consumption of 10.2 mW at 10-GHz operation.

A series of switchable resonators are proposed by incorporating the parasitic effects of two gallium nitride (GaN) high electron mobility transistor (HEMT) devices in this letter, based on which a broadband single-pole double-throw (SPDT) switch is presented with a bandpass response. As for on-chip switches, the ideal transistor is desired to act as a capacitor in its off-state but a resistor in its on-state. In conventional switch designs, the inductive effects of transistors are typically suppressed due to their detrimental impact on impedance matching and isolation. In contrast to this conventional approach, this study proposes a resonator-based design strategy that intentionally exploits and amplifies these inductive characteristics to construct two distinct GaN HEMT-integrated resonators. The first resonator employs the enhanced on-state inductance of a switching transistor combined with an MIM capacitor to form a series resonant network, enabling broadband impedance matching. The second resonator utilizes the large off-state capacitance of a power transistor and a short-circuited transmission line to establish a parallel resonant network. Leveraging the unique properties of these resonators, a broadband switch topology is accordingly proposed and experimentally validated. For demonstration, a SPDT switch is designed and fabricated in a 100nm GaN-on-Si process. The proposed switch operates from 16 to 33 GHz based on experimental measurements. Two transmission poles are observed in the passband. This result experimentally validates the GaN HEMT-based resonator design.

This paper presents a compact Doherty power amplifier (PA) featuring a single transformer balun. A novel envelope power detector architecture is introduced for high bandwidth (BW) adaptive biasing that is insensitive to process-voltage-temperature (PVT) variations. The measured PA attains a saturated power (Psat) exceeding 20.2 dBm and a power gain of 19.5 dB across the frequency range of 23-28 GHz. Moreover, it exhibits a peak power added efficiency (PAE) of 38% and a 6 dB power back-off (PBO) PAE of 27% at 25 GHz. The proposed adaptive biasing scheme enables a modulation BW of up to 800 MHz for a 64QAM signal. Under this setting, the average output power (Pavg) is measured at 11.3 dBm with an RMS error vector magnitude (EVM) of -24.5 dB and an average PAE of 15.5%. The PA is fabricated in Global Foundries 45nm-SOI technology with a compact area of 0.27mm2. To the best of the authors’ knowledge, this work is the first to demonstrate robust performance for Doherty PAs across PVT variations.

This paper presents an off-chip output capacitor (CO)-scalable (OCS) boost converter. The proposed OCS boost converter is possible to operate both with and without the off-chip CO. In addition, it operates in a whole conversion ratio (CR) range over 1 while maintaining a small current ripple of an inductor, resulting in a high efficiency with an inductor of which inductance is small, irrespective of the CO capacitance. The converter was fabricated in 130-nm BCD process and shows a peak efficiency of 96.68% at VIN = 5.5 V, VO = 7 V and IO=200mA which has the CR of 1.27.

A bi-directional near-ground-output low-side-input current-sensing amplifier (CSA) is fabricated in 65-nm CMOS. Two negative-feedback paths drive dual pMOS transistors to conduct an auto-switching bi-directional current detection with configurable unidirectional gains, which reduces the conventional switching-point distortions and doubles the sensing accuracy. A DC shifter based on a negative-feedback loop, avoids an input large current to benefit the sensing linearity, and optimizes the common-mode rejection ratio (CMRR). Various noise and offset suppression mechanisms are also utilized. Experimental results show that the proposed CSA achieves an offset voltage of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.58~\mu $ </tex-math></inline-formula>V, a noise level of 37.5 nV/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\surd $ </tex-math></inline-formula>Hz, and a CMRR up to 159 dB, with the power dissipation of 0.36 mW from a 1-V supply and an active area of 0.19 mm2. Reconfigurable or different unidirectional gains and near-ground input / output voltages are achieved, which are different from the existing designs.

This article presents a frequency quadrupler with 32% fractional bandwidth (66-92 GHz) and 5% peak power-added efficiency (PAE), capable of operating with an input power of 0 dBm. The quadrupler consisting of two cascaded frequency doublers uses a multi-port driven push-push complementary architecture for the first stage to generate differential signals for the second doubler with high fundamental harmonic rejection. The second doubler based on the NMOS-based push-push architecture uses gain enhancement to achieve a maximum conversion gain of -4 dB for the quadrupler. The quadrupler with an output saturation power (Psat) of -2.6 dBm achieves first-to third-harmonic rejections of more than 36 dBc across the 3-dB bandwidth. The compact quadrupler has a core area of 0.09 mm2, while consuming a DC power of 6.2 mW from a 0.8 V supply with an input power of 0 dBm at 20 GHz.

This paper presents a tri-well implementation of MOS capacitors designed to tackle the challenge of high parasitic capacitance. By serially connecting the three parasitic well junction capacitors between the three wells (N-Well, deep P-Well, and deep N-Well) and substrate (PSUB), the parasitic capacitance can be significantly decreased. A higher bias voltage is applied using a sufficiently large resistor to further reduce parasitic capacitance. Furthermore, we also present a simple and effective method for testing very small parasitic capacitance using off-chip inverters. The test chip was fabricated using the 180nm BCD process. The measurement results indicate that the ratio of parasitic to flying capacitance can be reduced to as low as 0.67% for 1.8V MOS capacitors through series-connected tri-well junctions with effective biasing while only increasing a 7.7% the chip area overhead compared to the dual-well junctions.