For many years, advancements in integrated circuit design have been driven by the pursuit of higher performance and lower cost. However, power consumption has increasingly limited the maximum achievable performance. At the same time, the rise of portable, wireless, wearable, and implantable devices has pushed designers to minimize energy use as much as possible. Over the past 35 years, researchers at UC Berkeley have led the field in low-power design, consistently developing and testing innovative ideas. This paper presents several of their contributions across the domains of digital, mixed-signal, and RF design.

Major technological innovation can arise either from breakthrough discoveries or from a visionary understanding of what becomes possible as technology evolves in combination with a methodology that leverages those developments. While breakthroughs often emerge from deep and focused exploration, visionary innovation typically relies on a meet-in-the-middle approach that integrates diverse disciplines to achieve an overarching goal. This is the essence of system-level design. By its very nature, it demands collaboration among researchers with varied expertise, usually brought together within organizations such as centers or institutes to pursue a common mission. To illustrate this point, we highlight several successful approaches in which Jan Rabaey has played a central role.

One often-heard comment about academic research is that it is too incremental and only marginally improving on the state-of-the-art. And indeed, we as researchers often tend to follow the wave of the day, and even worse trail it. To get away from this incrementalism, consider an alternative approach. Imaging or dream of how the future may look like - A prediction sustained by educated guesses informed by science, roadmaps and technology insights. From there we can work backwards to identify the big hurdles that need to be overcome to realize that future and let this guide our research. It is exciting and visionary. We call it <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">reverse time machines</i>.

As demand grows for multigigabit data links, high-resolution radar, and precision sensing, operating frequencies are being driven deep into the sub-terahertz (sub-THz) spectrum, where the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i>- and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</i>-bands (110–220 GHz) offer immense bandwidth (BW). However, operating at these frequencies with CMOS silicon technologies reveals several fundamental physical limitations, including limited breakdown voltage, low intrinsic gain, dominant parasitics, and significant passive losses. This article brings together different design methodologies that push these limits and expand the achievable power, gain, and BW of CMOS power amplifiers (PAs) operating near <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${f}_{\max}$</tex-math></inline-formula> The first approach revisits the concept of transistor stacking from a large-signal modeling perspective. By analytically accounting for all parasitic elements and the intrinsic delay of each device, a systematic framework is developed to determine the optimum input, output, and gate impedances for every transistor in the stack. A 45-nm SOI prototype that combines multiple stacked stages through a low-loss 4:1 combiner demonstrates 18.7 dBm saturated output power and 4.8% power-added efficiency (PAE) at 200 GHz, an example of how careful modeling can turn CMOS voltage limits into a scalable power generation strategy. The second methodology focuses on gain enhancement through embedding. At sub-THz frequencies, where matching-network losses can rival transistor gain, a passive feedback network is introduced and tuned on a “gain plane” that maps equi-gain and equi-load-conductance contours. This graphical design tool allows the simultaneous optimization of gain and output power. Implemented in a 65-nm CMOS 2 × 8 cell amplifier, the embedded approach achieves 19.5 dB gain and 9.4 dBm saturated power at 200 GHz, showing how modest feedback can recover otherwise-lost gain and extend usable output levels. The third technique, reverse-feedback amplification, breaks the BW barrier. By introducing a controlled amount of negative resistance into each amplifier cell, a distributed line is formed that supports constructive wave propagation and continuous power addition without interstage matching. Two 45-nm CMOS <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</i>-band amplifiers fabricated using this principle deliver up to 20.4 dB gain and 3.8% PAE across a 156- to 194-GHz 3-dB BW. Together, these methodologies, large-signal stacking, gain plane embedding, and distributed reverse feedback, demonstrate how thoughtful circuit architectures can overcome fundamental device limits to achieve high-power, high-efficiency, and broadband amplification in standard CMOS.