Through exploiting decentralized data from multi-source Internet-of-Things (IoT) devices, federated learning (FL) can accomplish the training of deep neural network (DNN) models in a privacy-preserving manner to provide premium intelligent services. Due to portability considerations, most IoT devices are computing-constrained which cannot afford frequent DNN model training in FL. Existing approaches use model compression techniques to reduce computing cost of IoT devices, whereas accuracy degradation is inevitably incurred. To address this challenge, we propose an elastic federated learning collaboration framework, namely EFLCF, to accommodate limited computing resources of IoT devices. Specifically, we first design an FL-oriented elastic neural network model with multiple-width subnets, and couple it with an FL device-server collaboration framework to form EFLCF, thereby releasing computing cost pressure of IoT devices. We then develop a freezing-assisted wide-to-narrow training mechanism to realize efficient device-server distributed training and further reduce device computing cost. Finally, we design an entropy-based narrow-to-wide elastic inference mechanism to decrease computing cost of inference without compromising accuracy. Experiments demonstrate that compared to well-known benchmarks, our EFLCF can reduce up to 97.65% device computing cost and improve up to 48.3% accuracy in training, while reducing up to 42.5% computing cost in inference.

To tackle power management challenges in deep neural networks (DNNs), dynamic voltage and frequency scaling (DVFS) has gained attention for its ability to enhance energy efficiency without modifying DNN structures. However, current DVFS methods, which rely on historical data such as processor utilization and task load, suffer from issues like frequency ping-pong, response lag, and limited generalizability. These challenges are exacerbated by real-world scenarios that prioritize time, energy, or energy efficiency differently, making it even harder for existing methods to effectively configure DVFS under such multi-objective constraints or trade-offs. This paper presents MultiLens, a multi-objective adaptive DVFS framework. First, we propose a power-sensitive feature extraction method along with multi-objective constraint modeling to characterize DNN inference behavior. Second, critical power blocks are then identified through clustering based on inference behavior similarity, enabling adaptive DVFS instrumentation point settings. Moreover, to enhance the adaptability of multiple platforms and the flexibility of multiple scenarios, MultiLens integrates a complete deployment process. Experimental results demonstrate the effectiveness of the MultiLens in optimizing energy efficiency across different hardware platforms and deployment scenarios.

PHOTON-Beetle is an authenticated encryption scheme, which was a finalist in the NIST’s call for standardization in the area of lightweight cryptography (LWC). There are certain difficulties while executing known fault attacks on PHOTON-Beetle in the real world. One of the attacks is in the random fault model, but it requires 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">37.15</sup> faults, which makes it difficult to implement in practice. Other attacks require fewer faults (2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9.32</sup> and 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11.5</sup>) but rely on the bit-fault models, which necessitates expensive tools and detailed information about the implementation. In this paper, we bridge this gap by presenting an attack that is based on a realistic fault model that requires only 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup>. We employ a new fault attack technique called linked ineffective fault attack (LIFA). Our attack does not require knowing the plaintext or the corresponding ciphertext. Compared to conventional key-recovery techniques, we provide a highly efficient algebraic method for obtaining the secret key. Furthermore, we introduce linked effective fault analysis (LEFA) and show that, in a noisy environment, LEFA performs significantly better than LIFA in attacking the PHOTON-Beetle while maintaining the basic assumptions of LIFA. We verify our attack using several simulations, as well as conducting practical experiments in the ATmega328P against the publicly available PHOTON-Beetle implementation made available by the designers.

In heterogeneous multi-core systems, efficiently allocating tasks to cores is a key challenge due to the complexity of hardware architectures and the dynamic nature of workloads. System states and task behaviors are inherently partially observable due to limited accessible information about interactions among tasks and shared resources, which complicates the prediction and management of execution times and resource contention. Moreover, uncertainties such as unpredictable execution times and variable workloads, combined with the challenge of prioritising high-criticality tasks while maintaining overall system performance and ensuring fairness in the execution of lowcriticality tasks, necessitate the use of sophisticated allocation strategies. We propose a novel approach which embraces the uncertainty of modern systems. Partially Observable Markov Decision Processes (POMDP) and Active Inference are used to minimise uncertainty and optimise allocation decisions. By representing uncertainties within the POMDP framework, our method enables probabilistic predictions of task behaviours and system states. Active Inference refines these predictions and adapts decisions dynamically, handling workload variability and system changes such as adding new tasks. Our methodology emphasises application-layer scheduling as opposed to kernellevel modifications, thereby giving our approach both platform awareness and deployment flexibility. Moreover, the capacity for offline training mitigates the adverse effects of online updates on the accuracy of target platform comprehension. Experimental results demonstrate superior performance over baseline approaches, enhancing system efficiency and resource utilisation by incorporating task criticality awareness, even in the presence of uncertainties and partial observability.

ASIC accelerators have emerged as vital solutions to deploy various AI workloads, especially in resource-constrained edge scenarios. Existing analytical models for guiding the architectural exploration of these accelerators focus solely on performance and energy efficiency metrics while overlooking the carbon cost. In contrast, existing carbon cost models focus on analyzing specific hardware configurations but lack the support for exploration of the optimal architecture choices and the trade-off analysis between performance and carbon cost. To fill this gap, this paper aims to analyze the impact of different architecture configurations from both the performance and carbon perspectives, exploring the trade-off between the performance and carbon cost for AI accelerator design. For this purpose, we first built an analytical model, named <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CarbonSpot</i>, capable of modeling and estimating both performance and carbon cost for any accelerator architecture in the design space. Then, by benchmarking the overhead of these AI accelerators under MLPerf-Tiny and MLPerf-Mobile workloads, we show that architectures solely optimized for performance and energy efficiency produce 58× more carbon emissions than designs designed for the highest carbon efficiency. Importantly, co-optimized architectural choices exist, with only <20% drop in performance and <6% overhead in carbon costs when compared to the respective best cases optimized for either maximum performance or minimal carbon impact. The model is open-sourced at: https://github.com/KULeuven-MICAS/carbonspot.

This paper proposes an uncertainty quantification (UQ)-incorporated design optimization technique that integrates UQ considering the statistical characteristics of sensing margin with machine learning (ML) for the design of bitline sense amplifiers (BLSAs) in dynamic random access memory (DRAM), including offset compensation operation. The increased offset due to process variation exacerbated by device scaling degrades the reliability of DRAM read operations, making quantitative analysis of process variation essential. Conventional Monte Carlo (MC)-based UQ analysis provides high accuracy but requires extensive simulation costs. Accordingly, this study systematically defines key input and output variables for conventional BLSA and two representative offset compensation BLSA structures, introduces Sobol sequence-based quasi-Monte Carlo (QMC) sampling to improve simulation efficiency, and generalizes the Standard UQ methodology to predict statistical distributions of circuit performance parameters under process variation. Furthermore, a 3-Stage UQ algorithm that sequentially learns nominal, mean, and standard deviation values is proposed to enhance the efficiency of ML model training. HSPICE simulation results based on the TSMC 65 nm process demonstrated that the proposed 3-Stage UQ method reduced the simulation time required for ML training data generation by an average of 43% compared to the Standard UQ method and achieved excellent prediction performance even in data-limited environments. Additionally, design optimization combined with Bayesian Optimization (BO) confirmed performance improvements across all circuit structures. The methodology presented in this study enables effective process variation-aware optimization for DRAM designs requiring high reliability and yield, and is expected to contribute to next-generation memory circuit design automation.

Device design using Machine Learning has been used in the semiconductor industry over the past ten years. However, the generation of the training data set for precise predictions using this technique remains burdensome. Addressing this, in this work, we propose eight sample-efficient techniques to train the Deep Neural Network (DNN) based surrogate models that emulate Technology Computer-Aided Design (TCAD). We showcase their efficacy by predicting off-state breakdown voltage (BVDS,off) and specific on-resistance (Rsp) of a Laterally Diffused Metal Oxide Semiconductor Field-effect Transistor (LDMOSFET). Our findings highlight the potential for 38% reduction in training dataset size while maintaining a strong predictive baseline accuracy. Specifically, the Diverse Representative-Query-by-Committee (DR-QBC) technique works best yielding 6.5% Euclidean Norm of Prediction Error (ENPE). We also demonstrate an inverse design framework by leveraging the same surrogate model with Differential Evolution (DE) and Bayesian Optimizer (BO). It mimics the role of a device design engineer by optimizing the values of structural parameters of the LDMOS transistors such that the desired BVDS,off is attained while minimizing Rsp.

With the increasing demand for higher bandwidth and frequency in high-speed digital systems, the interference of common-mode (CM) noise in differential signal transmission has become more severe. Common-mode suppression filters (CMF) were proposed to solve this issue, but their design process typically relies on empirical parameter tuning with extensive electromagnetic simulations, which not only increases design costs but also limits efficiency and flexibility. In this paper, a transformer-based inverse design method for CMFs is proposed for the first time, and it can eliminate the need for empirical parameter adjustments by automatically predicting the targeted geometric parameters, thereby improving the design efficiency. In addition, to address the problem of imbalanced data distribution, the multilabel synthetic minority over-sampling technique (MLSMOTE), which can enhance the data representation in sparse sample regions, is implemented. Further validation on tunable CMFs confirms that the proposed inverse design method has broad applicability. The experimental results demonstrate that the proposed inverse design method can accurately predict the geometric parameters and improve the efficiency, thereby providing an innovative solution for the design and applications of CMFs.

With the growth of circuit size and FPGA complexity, routing becomes an increasingly complicated and timeconsuming task for modern FPGAs. To accelerate FPGA routing, many parallel algorithms have been proposed to perform concurrent routing for multiple independent nets that have no overlaps in routing resources. The requirement on net independence can help reduce the synchronization overhead by circumventing the data race in different threads, but it will significantly limit the parallelism due to the large number of overlapping nets in modern circuit designs. Therefore, to strive for large-scale parallelism, it is a promising direction to explore the parallel routing for overlapping nets. In this work, we first propose a parallel overlap-tolerant router, called Potter, including the runtimefirst Potter-R and the stability-first Potter-S. Potter-R employs a partitioning-based recursive net scheduling algorithm to divide nets into balanced groups while minimizing resource overlaps among net groups. These net groups are then routed independently and concurrently. A novel factor updating mechanism is proposed to accelerate solving congestion in the negotiation-based routing algorithm. Furthermore, based on Potter-R, we devise an efficient synchronization strategy in Potter-S to maintain determinism when concurrently routing overlapping nets. An enhanced clustering-based net scheduling method is developed to minimize overlaps among different net groups. In the FPGA24 routing contest benchmarks, our proposed method outperforms the state-of-the-art methods in both running time and wire length. Potter-R not only achieves the largest 12.34× speedup to the sequential router RWRoute but also has the best 4% improvements on wire length. Furthermore, compared with the fastest deterministic parallel router CUFR, Potter-S can