NVM provides a more generalized high-density memory media with DRAM-like performance and non-volatile nature to provide persistent data accesses to computing devices. Due to the poor write tolerance of NVM, wear-leveling strategies are essential in NVM. We find that the remapping table accesses become a neglected performance bottleneck when deploying wear-leveling strategies in NVM controllers, and contiguity-based CPU address mapping caching optimization strategies cannot be adapted due to the randomized mappings introduced by wear-leveling strategies. In this paper, we present RTCache, an efficient caching mechanism designed to accelerate access performance of the wear-leveling remapping table in NVM controllers. We propose a two-level mapping cache to enhance the cache utilization, consequently improving the cache hit ratio. Notably, RTCache incorporates a victim cache to improve the efficiency of RTCache for discretely accessed pages. Furthermore, RTCache adopts a cache-friendly remapping table memory structure, mitigating the challenges posed by access amplification due to RTCache misses. Experimental results show that RTCache can significantly improve the performance of NVM with wear-leveling strategies, and the negative impact on the system performance is reduced to an acceptable level.

Hybrid optimization is emerging as a promising approach for enhancing logic synthesis by combining multiple logic optimization methods. This paper introduces CHOP, a novel framework that leverages vertex-level feature extraction and optimization-aware clustering to achieve significant improvements in the efficiency and quality of logic synthesis. Unlike existing cluster-level approaches that follow a “partition-then-predict” paradigm, CHOP operates under a “predict-then-partition” approach where the optimization method most appropriate for a given circuit vertex is determined by analyzing its local structural and functional context. To capitalize on this insight, CHOP extracts a subgraph centered on each vertex and calculates its circuit cost, which serves as a vertex feature for the subsequent circuit partitioning process. Furthermore, we introduce a self-supervised prediction model to obtain these vertex features efficiently. Following circuit partitioning, CHOP determines the optimization method for each partition and then iteratively applies these methods to derive the optimized circuit. The experimental results from logic optimization and LUT mapping tasks on the EPFL benchmark demonstrate the effectiveness and efficiency of CHOP.

For precision motion control systems, real-time feedforward compensation is indispensable, yet its implementation is constrained by latency, computational/storage hardware resources. Classic approaches, including online model-based feedforward and iterative learning control feedforward, fail to balance accuracy and generalization. Although offline neural network feedforward (NN-FF) has emerged as a potent alternative, in-depth investigation into its real-time deployment is still lacking. Furthermore, even state-of-the-art, offline recurrent NN-FF (RNN-FF) models impose substantial demands on hardware resources (due to large parameters and inherent sequential processing), making them less suitable for efficient real-time implementation. This paper proposes a generalized hardware-model co-optimization framework for real-time NN-FF. Specifically, we develop Motion Residual Convolution (MRC): a compact CNN-based model with high accuracy, strong generalization, lightweight design, and inherent parallelism for latency reduction. Correspondingly, we construct an accelerator core with 10 vector multiply-accumulate (VMAC) units for multi-filter parallel processing. For two scenarios with distinct priorities, specifically the resource-constrained and the latency-constrained, we adopt spatial feedforward acceleration engine (SFAE) and temporal feedforward acceleration engine (TFAE), respectively. SFAE maximizes throughput via independent VMAC arrays per convolutional layer, while TFAE optimizes resource utilization through time-multiplexing a single VMAC array across layers. Experiments indicate MRC outperforms RNN-based counterparts in accuracy, using <1% of their storage and computational resources. The proposed accelerators achieve high energy efficiency with compact hardware resources, benefiting from the lightweight MRC model. Moreover, both accelerators achieve effective trade-offs: compared with TFAE, SFAE consumes 6.9–40.9% more key logic resources and 3.1% more power but delivers an average 61× execution speedup, achieving an energy efficiency of 222.2 GOPS/W.

Recent progress in video generation models (VGMs) has enabled long video generation with strong visual fidelity. VGM architectures have evolved from decomposed 2D attention (e.g., separate spatial/temporal attention) to 3D full attention that jointly processes all frames. However, inference latency remains a major bottleneck due to algorithmic and architectural inefficiencies. Differential methods have become a potential solution by leveraging sparsity to reduce computation. However, existing studies face two challenges: <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Challenge-1</i>: The existing differential methods fail to identify the weakly connected parts in VGM that can be approximately calculated, leading to many potential redundant computations or severe impacts on generation quality (> 5% loss). <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Challenge-2</i>: The traditional architecture fails to effectively utilize the unique redundancy distribution (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i.e</i>., column-concentrated pattern) in compressed VGMs. To address the above challenges, we propose <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DiffAttn</i>, a sparse attention architecture for video generation with differential approximation. Building on our prior conference work (ViDA), <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DiffAttn</i> generalizes differential computing to 3D full attention and strengthens architectural support to exploit the resulting column-concentrated sparsity. It combines three tightly coupled techniques. (1) Spatial information-guided differential estimation method utilizes spatial information to estimate the weakly connected regions in attention computation, which reduces the attention computation by 66.84%. (2) Column-concentrated computing architecture fully leverages the unique column-concentrated sparsity characteristics in the compressed VGMs, which achieves 1.52× speedup over a fully dense architecture. (3) Sparsity-aware inter-layer dataflow dynamically adjusts the workload ratio between the two cores by analyzing layer-wise sparsity and column distribution at runtime, improving the utilization by 36.33%. Experiments on advanced VGMs (e.g., CogVideoX1.5, OpenSora2.0) show that <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DiffAttn</i> achieves up to 2.62× and 1.89× end-to-end speedup and 3.14×/ and 2.87× energy efficiency improvement over NVIDIA A800 GPU and advanced VGM accelerator, respectively.

We present a stable embedded discontinuous Galerkin (EDG) method for scalable electrothermal simulation of 3D semiconductor devices. The framework extends the robust hybridized discontinuous Galerkin method developed for purely electric paradigm to resolve fully coupled electrothermal drift-diffusion equations, addressing a critical gap in existing harmonic-averaging formulations that lack non-isothermal current modeling. It is believed that for the first time, we derive a consistent discretization of thermally coupled current terms within the EDG scheme, ensuring stability under strong convection and Joule heating. A parallel solver is further developed and implemented via the JAUMIN framework using domain decomposition, enabling extreme-scale 3D simulations of semiconductor devices. The validations on p-n junctions, NLDMOSFET and multi-finger FinFET demonstrate superior Newton convergence and comparable accuracy in comparison with that of commercial software COMSOL. It can achieve 79.2% strong scaling efficiency (20×cores) and 59.0% weak scaling efficiency (8× problem size) in the 8-Finger FinFET electrothermal simulations.

The brain emotional learning network offers several advantages when compared to traditional neural networks. It features a simpler structure, low computational complexity, and fast training speed. These characteristics make it ideal for applications like pattern recognition, data classification, and intelligent control. However, current brain emotional learning networks, including their modified networks, are not capable of recognizing or classifying data in complex environments. To address this issue, this paper proposes a brain emotional learning network with an attention mechanism that strengthens the processing of key information while suppressing interfering information, thereby enabling the network to recognize data within complex environments. Furthermore, software implementation of neural networks often experiences slow computing speeds due to the separation of storage and computation in traditional von Neumann computers. To combat this issue, the paper presents a hardware circuit implementation of the attention mechanism-based brain emotional learning network using memristors. Finally, the designed in-memory computing neural network has been successfully applied to the recognition of traffic signs within complex environments, and has achieved accurate and rapid recognition.

Memristor-based crossbar architectures have proven highly effective for matrix vector multiplication (MVM) operations, making them a promising solution for accelerating the MVMs widely used in precoding algorithms for multiple input multiple output (MIMO) wireless communication systems. However, real-world implementation of memristor-based computing systems face challenges due to commonly observed non-idealities in both the devices themselves and the circuits they’re built into. To facilitate a rapid design flow and investigate the impact of non-idealities, an integrated open-source simulation framework MemMIMO is developed. The simulation framework estimates the accuracy and hardware performance of the computing system, offering a variety of flexible design options. MemMIMO integrates a behavioral model of the mix-signal architecture with a digital front-end. There are three major building blocks in MemMIMO: the device fitting block, the mapping block, and the performance estimation block. These blocks work together to map the complex MVMs in precoding algorithms for MIMO systems to crossbar-based architectures that incorporate memristor models characterized by physical device behavior. Using two typical use cases targeting six-generation (6G) massive MIMO communication as case studies, MemMIMO is used to model different memristor devices, explore the impact of non-idealities on system accuracy, and benchmark circuit-level performance metrics including area, speed, and power.

Manycore platforms have emerged as a promising candidate to meet the increasing computation demand in high-performance computing (HPC). Networks-on-Chip (NoC) have proposed appropriate on-chip communication solutions for manycore platforms. However, the increase in the number of cores and the size of cache in a single chip raises the power dissipation of NoC, potentially impacting data communication performance. The primary source of power dissipation in NoC is the switching activity of data bits transmitted through data links. In this study, we introduce an analytical method, based on information theory, to assess data representation or coding methods from the perspectives of the switching activity of data bits and the length of codewords used for data symbols. Subsequently, we propose a lightweight yet efficient Low-Power Code Reordering (LPCR) technique, that can be integrated into existing coding methods to decrease power consumption. The comprehensive evaluations presented in this paper demonstrate that our LPCR method, reduces link power consumption through reducing the switching activity of data bits up to 13.2%, on average 8.8%, while increases the number of data bits by less than 4.9%, this decreases link energy consumption by 9.9% when applied to the coding methods which aim to minimize the number of data bits (e.g., Huffman coding). However, LPCR does not change the number of data bits when implemented on the Binary coding and, decreases the number of bits up to 12% when implemented on the Most Frequent Least Power (MFLP) method. LPCR impose a very low time and memory overhead at runtime. It needs a data array ranging from 256B for Binary to 32KB for MFLP methods and executes one extra command to read codewords from the array.

The accurate extraction of interconnect parasitic capacitance is a critical issue for designing VLSI circuits. To improve the efficiency of parasitic capacitance extraction, we present in this paper an adaptive incremental learning (AIL) strategy to build the parasitic capacitance extraction pattern model. The proposed model is a deep neural network (DNN) trained using adaptive incremental learning, or AIL-DNN. The key ideas are as follows: Firstly, the parametric space is divided into several subspaces called regions. And then a small number of training samples and test data are collected by Latin hypercube sampling (LHS); Secondly, a DNN model is trained and tested. The regions with large prediction errors are determined based on the average relative errors of test, which are called the training ineffective regions; Then, according to the ineffective regions, the sampling density is adjusted, that is, a new training dataset is prepared by adaptive resampling; Finally, incremental learning (IL) is used to make the DNN train new samples and update the network. The procedure of adaptive resampling, training and testing iterates until the test error reaches the predefined prediction accuracy. The proposed AIL-DNN can improve the efficiency and accuracy of DNN training with a reduced number of samples, and the trained DNN model can be used for the rapid extraction of parasitic capacitance. In this work, the prediction results of AIL-DNN and of the traditional DNN for two given interconnect patterns are compared. The results show that the size of training dataset required by AIL-DNN is about 20% of that of the traditional DNN with the similar accuracy. This significantly reduces the computational cost and time of dataset preparation.