In modern DRAM design, IR-drop has emerged as a critical factor leading to operation failures, primarily due to reduced metal resources and increased supply current demands. Consequently, estimating and addressing IR-drop throughout the DRAM design process has become a crucial sign-off consideration. The proposed comprehensive methodology for the power delivery network (PDN) includes accurate and efficient estimation at two key stages: early in the design process (Early PDN) and during post-physical design sign-off validation (Iterative PDN). The Early PDN approach employs simplified modeling to achieve reasonable accuracy, serving as a guideline for the initial PDN design. Subsequently, the Iterative PDN method provides a fast yet detailed analysis of the entire DRAM, including the PDN, ensuring it is suitable for final sign-off. By applying this methodology, PDN behavior can be effectively predicted and optimized, ensuring robustness. This enhances the reliability and performance of DRAM designs.

Hotspot detection is a crucial step in ensuring the manufacturability of integrated circuits, as it seeks to identify potential defects in the layout. Pattern matching methods have been widely used to accelerate the detection of these defects. However, they often struggle with complicated deviations. Image-based machine learning methods were introduced to confront this challenge, but they often involved distorted information extraction and incurred significant runtime overhead. In this article, we introduce a novel detection framework based on the modified transitive closure graph (MTCG). By applying the concept of MTCG, the layout can be accurately modeled as a heterograph. The embeddings of these heterographs are extracted using an optimized lightweight 3-hop message-passing graph neural network (GNN) and subsequently utilized for classification. Furthermore, a dynamic edge transformation method based on the properties of MTCG is proposed for data augmentation. The proposed method is evaluated with datasets from ICCAD 2012 and ICCAD 2019, demonstrating outstanding performance in recall and false alarm, along with a significantly decreased inference time.

Approximate computing is emerging as a promising approach to devising energy-efficient IoT systems by exploiting the inherent error-tolerant nature of various applications. In this article, we present Approx-T, to tackle several major challenges according to the prior state-of-the-art (SOTA) approximate multiplication units (AMUs)—lack of comprehensive optimization formulation, asymmetric error distribution, nonadjustable runtime precision, and exponentially growing area complexity when adding up error compensation levels. We innovatively conduct an in-depth study on approximate multiplier via Taylor-expansion to address these issues. 1) Incorporate the Taylor’s theorem into the design concept of approximate arithmetic multipliers. 2) Leverage the inherent symmetrical error distribution of Taylor series to conduct unbiased approximations. 3) Present a runtime configurable error compensation architecture with low-complexity arithmetic operations. We implemented both approximate unsigned and signed integer and floating multiplication arithmetic units and compared with the SOTA works. The experimental results demonstrate that Approx-T surpasses other designs in all metrics, encompassing precision, area utilization, and power consumption. Furthermore, when deployed on an embedded field programmable gate array platform to assess a spectrum of edge computing tasks, Approx-T showcases remarkable performance. Particularly in CNN applications, it achieves up to a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10.7\times $ </tex-math></inline-formula> enhancement in energy efficiency, while maintaining negligible impact on accuracy.

The runtime and accuracy of interconnect parasitic extraction are becoming increasingly crucial for integrated circuit design in advanced manufacturing processes. In this study, we propose a novel method of capacitance matching that maps low-level features to high-level spaces, which reduces feature dimensions without losing essential information and provides a compact form for the geometric features of 2-D patterns in full-chip capacitance extraction. Furthermore, we are introducing a creative labeling strategy that eliminates the requirement for separate task-specific heads or different input representations. This innovative approach enables simultaneous data processing for both total and coupling capacitance tasks, leading to a significant reduction of complexities. Our experiments demonstrate that our entire feature representation and pattern-matching algorithm delivers exceptional accuracy, improved runtime, providing an efficient solution for large-scale capacitance extraction.

Power efficiency is a critical design objective in modern microprocessor design. To evaluate the impact of architectural-level design decisions, an accurate yet efficient architecture-level power model is desired. However, widely adopted analytical power models like McPAT and Wattch have been criticized for their unreliable accuracy, while machine learning (ML) methods like McPAT-Calib rely on sufficient known designs for training and perform poorly when available designs are limited, which is the case in realistic scenarios. In this work, we propose PANDA, an innovative architecture-level solution that combines the advantages of analytical and ML power models. It achieves unprecedented high accuracy on unknown new designs even when there are very limited designs for training. Besides being an excellent average power model, we also extend PANDA to support the time-based power trace prediction, which can enable the analysis of peak power, power fluctuations, and voltage fluctuation. This is highly challenging at the architecture level. Other qualities, such as area, performance, and energy accurately, can also be supported. In addition to single design quality, PANDA can model the tradeoffs among different design qualities, such as the tradeoff between power and timing, by predicting the Pareto-optimal curve. Finally, PANDA can further support power prediction for unknown new technology nodes. Our experiment shows that, for average power prediction, our method can achieve high accuracy with a correlation coefficient R of 0.99 and mean absolute percentage error (MAPE) of 7.91% even when only one configuration is known, outperforming McPAT-Calib which has R of -0.24 and MAPE of 35.96%. For time-based power trace prediction, our method can achieve a low MAPE of 4.34%, outperforming the state-of-the-art method Powertrain which has a MAPE of 53.8%.

Advanced digital microfluidic biochips based on technologies such as micro-electrode-dot-array (MEDA) and active matrix (AM) provide enhanced functionality compared to conventional biochips. Owing to the larger ratio of droplet size to electrode size, these platforms allow finer control of droplets and diagonal movement. Additionally, they allow dynamic grouping of micro-electrodes to form subsystems that can perform fluidic operations. Shape morphing is a key feature of MEDA/AM biochips that results in faster fluidic operations, thereby improving the efficiency of bioassays. To establish the benefits of shape morphing, we first numerically simulate the shape morphing operation. We employ a simplified 2-D flow model incorporating interface tracking through a level-set method to numerically simulate shape morphing induced by micro-electrode actuation. We also validate our numerical results with COMSOL simulations and experiments performed on MEDA/AM biochips. The validated shape morphing operations are subsequently used to optimize droplet routing for benchmark bioassays. We propose an algorithm to significantly reduce the size of the routing problem and the time needed to solve it. With the help of this improved approach, we show that droplet morphing operations reduce the time needed to complete bioassays.

As a new generation of flow-based microfluidics, Fully Programmable Valve Array (FPVA) biochips have gained widespread adoption as a biochemical experimental platform, thanks to their enhanced programmability and flexibility. Environmental and human factors, however, often introduce physical faults during the manufacturing process such as channel blockage and leakage, which, undoubtedly, can affect the results of bioassays and even cause execution failure. In this paper, we focus on the fault-tolerant co-design of flow and control layers in FPVA biochips for the first time. For the flow layer, three dynamic fault-tolerant techniques, i.e., a cell function conversion method, a bidirectional redundancy scheme, and a fault mapping method, are presented and integrated into the device placement and flow routing stages. As a consequence, we further realize an efficient and effective fault-tolerance-oriented physical design method, thus ensuring the robustness of chip architecture and correctness of assay outcomes. For the control layer, we design another three fault-tolerant techniques including a series duplication scheme of leakage valves, allocation and merging rules of backup valves, and a logic conflict-aware adjustment strategy of redundant architecture. Based on these techniques, we construct a fault-tolerant control system to realize dynamic recovery of control signals. Experimental results on multiple test cases demonstrate that the proposed method can produce optimized fault-tolerant FPVA architectures with low fabrication cost, high execution efficiency, and high fault-tolerance success rate.

Zero-knowledge proof (ZKP) is a widely used privacy-preserving technology, where multiscalar multiplication (MSM) accounts for over 70% of the computational workload. The acceleration of MSM can enhance the overall performance of ZKP, making it a focal point of community attention. However, in practical applications involving the deployment of multiple MSM accelerators, existing designs often overlook strategies for optimizing bandwidth and area efficiency. To address this, we propose Myosotis, an efficiently pipelined and parameterized MSM architecture. By sharing input data and allocating cache effectively, it mitigates average transmission bandwidth in runtime. Myosotis also supports the use of multiple point addition (PADD) units to achieve performance gains, balancing area overhead and latency for improved area efficiency. Different parameter selection enables a tradeoff between the performance, area, and bandwidth of the MSM accelerator. When benchmarking with MSM degrees between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{18}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{26}$ </tex-math></inline-formula>, our proposed baseline design achieves up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.32\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.72\times $ </tex-math></inline-formula> speedups over state-of-the-art FPGA and ASIC designs. Compared to the baseline, Myosotis with two window MSMs and one PADD unit reduces bandwidth demand by 43% while maintaining similar area and latency. On the other hand, Myosotis with three window MSMs and two PADD units decreases latency by 43% and bandwidth by 17%, with only a 9% area increase.