In an era marked by technological innovation, visual applications have become ubiquitous in everyday life. Harnessing the power of computer vision, these applications process and interpret video data from edge cameras, facilitating tasks such as object detection and vehicle counting. Yet, implementing complex deep learning models on cameras with limited computational capacity poses significant challenges. Furthermore, the bandwidth constraints and fluctuating nature of wide-area networks present substantial difficulties for video analysis systems dependent on cloud computing. This paper first characterizes the relationship between different parameter combinations (such as frame rate and resolution) and video analysis accuracy through offline analysis. It proposes a video stream analysis configuration selection scheme, SPStream, for slowly changing scenes, and a configuration file switching strategy, SPStream+, for rapidly changing scenes. These strategies use idle resources at the camera edge end to select the optimal configuration in real-time, adjust video encoding quality, and dynamically switch configuration files based on the changing states of object motion. Finally, a real-time video stream analysis system for vehicle counting and pedestrian detection suitable for both scenarios is designed, which saves bandwidth to the greatest extent while meeting the accuracy requirements of users and achieving high accuracy of video analysis.

Logarithmic multiplier (LM) converts fixed-point (FxP) input operands to logarithmic numbers and performs multiplication with simple shift and addition operations, which achieves distinct power reduction, yet with significant single-sided errors. This paper proposes to fuse error compensation with logarithmic conversion by using customized look-up tables (LUTs). To avoid the use of large LUTs, partition strategies are designed for the optimization of LUTs. In addition, to effectively balance the accuracy and hardware costs, two iterative algorithms are proposed for generating precision-configurable LUTs. Based on the optimized LUTs, high-accuracy and low-power approximate LMs (LUT-ALMs) are constructed for 8-bit and 16-bit multiplications. Furthermore, to enhance the flexibility of data type and bit width, a mixed-mode LM (MM-ALM) supporting eight multiplication modes is devised. Compared with the exact 8-bit signed multiplier from Synopsys DesignWare (DW) library (DW-Exact), LUT-ALMs show up to 30.96% and 23.99% reductions in the power-delay product (PDP) and area-delay product (ADP), respectively, with a mean relative error distance (MRED) of 3.45%. Compared with state-of-the-art approximate 8- bit signed multipliers, LUT-ALMs form the Pareto front in terms of PDP and MRED. For 16-bit multiplication, LUT-ALMs obtain up to 70.90% and 62.13% savings in PDP and ADP with a MRED of 2.75%, compared with the corresponding DW-Exact. Compared with the corresponding mixed-mode exact multiplier constructed of DW multipliers, MM-ALM performing 8-bit multiplication achieves up to 57.44% and 47.99% reductions in PDP and ADP, respectively. When performing 4-bit multiplications, MM-ALM can save up to 37.16% savings in PDP. With lower hardware over-heads, LUT-ALMs and MM-ALM present comparable accuracy to the corresponding exact designs in the considered convolutional neural networks (CNNs) and image processing applications. The hardware description of the devised LMs is open-sourced at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://anonymous.4open.science/r/LUT-ALM-5FD1</uri>.

Ensuring atomic execution of cross-shard transactions is a fundamental challenge for sharded blockchains, particularly in scenarios demand coordination across multiple shards. However, existing solutions either rely on on-chain coordination, leading to high communication overhead, or leverage secure hardware for off-chain execution, imposing strong trust assumptions and reducing general applicability. To this end, we propose RollShard, a sharded blockchain that integrates stateless off-chain mechanism to efficiently process multi-shard transactions (MSTs). In RollShard, each MST is abstracted into a transaction DAG by the Sequencer Shard to ensure the authenticity of the transaction content and the correctness of its execution order. Batched MSTs are dispatched to off-chain executors, each of which simulates transaction logic using a virtual zero-state model integrate with a hierarchical state-delta tree (HSDT). The HSDT employs a Merkle Sum tree to precisely capture batched MSTs’ impact on per-shard account states. Based on the HSDT, the executor generates the zero-knowledge proof to attest the correctness of each shard’s state changes and global value conservation. The resulting net state deltas are then optimistically committed to the relevant shards without cross-shard coordination, reducing intra-shard coordination. We design a game-theoretic incentive mechanism to ensure rational behavior of off-chain executors, showing that honest execution forms a Nash equilibrium under collateral staking. Experimental results based on a prototype deployed in a local area network demonstrate that R<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OLL</small>S<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HARD</small> significantly outperforms two baseline coordination models proposed in ByShard, namely the Linear and Distributed designs. Specifically, under high workload, RollShard improves throughput by 44.9% and 158%, and reduces cross-shard latency by 38.9% and 42.1%, compared to the Linear and Distributed models, respectively.

Secure Multi-Party Computation (MPC) enables secure computation on private data. Many of today’s efficient MPC protocols need a representation of the evaluated function as circuit composed of Boolean or Lookup Tables (LUTs). To improve the practicality of MPC, we present SynCirc, a hardware synthesis framework optimized for MPC applications. Built on Verilog and the open-source tool Yosys-ABC, SynCirc introduces custom libraries and constraints for multi-input AND gates, achieving up to 3× reduction in multiplicative depth and online rounds compared to TinyGMW (Demmler et al., CCS’15). <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SynCirc also offers an expanded library of efficient building blocks like comparison, multiplexers and equality checks, and incorporates Boolean and LUT circuits. For these building blocks, we achieve improvements in multiplicative depth/online rounds between 22.3% and 66.7% over ShallowCC (Büscher et al., ESORICS’16). Our evaluation using the FLUTE framework (Brüggemann et al., IEEE S&amp;P’23) shows that SynCirc has 116× less online communication than the multi-input AND gate protocol of Trifecta (Faraji and Kerschbaum, PETS’23). <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SynCirc introduces new capabilities, including enhanced support for High-Level Synthesis (HLS) with the XLS tool, enabling developers to create secure functions in C/C++ without the need for expertise in hardware definition languages like Verilog. SynCirc is an open-source toolchain that democratizes secure computation, simplifies circuit synthesis, and makes advanced privacy-preserving technologies more accessible.

The lack of actionable guidance is a fundamental limitation in Action Quality Assessment (AQA), as traditional methods provide overall scores without offering specific insights for improvement. Moreover, existing interpretable approaches often rely on expensive supervised spatial annotations or yield noisy, unsigned saliency maps. To address these challenges, we propose Learning Interpretability Based Supervoxels (LIBS), a novel framework for generating instructional feedback. Distinguishing itself from fully supervised methods, LIBS employs an unsupervised soft-clustering mechanism to segment videos into coherent supervoxels without requiring pixel-level mask annotations. This allows for scalable, fine-grained spatio-temporal analysis while preserving action continuity. Furthermore, we introduce a sensitivity propensity analysis to quantify the contribution of each supervoxel. Unlike traditional attribution methods, this mechanism explicitly decomposes the quality score into positive (strengths) and negative (flaws) components, enabling the system to decode abstract scores into concrete, actionable instructions. Experimental validation across multiple datasets demonstrates that LIBS achieves superior interpretability and efficiency compared to state-of-the-art baselines, marking an improvement from diagnostic to instructional AQA applications.

With the proliferation of interconnection networks in mission-critical systems ranging from cloud computing infrastructures to large-scale data centers, the escalating structural complexity has intensified network vulnerability to malicious attacks and cyber warfare incidents. This article establishes a theoretical framework for evaluating network self-diagnostic capability through a novel <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</i>-extra <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</i>-component diagnosability metric, denoted as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\widehat{ec}_{r}^{h}(G)$</tex-math></inline-formula>, which quantifies a network’s resilience under compound fault patterns. The proposed metric requires that after removing specific nodes, the remaining subgraph is required to preserve at least <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</i> connected components where every component maintains a node count exceeding <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</i>. Through rigorous combinatorial analysis, we derive closed-form expressions for star networks <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$S_{n}$</tex-math></inline-formula>, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\widehat{ec}_{2}^{1}(S_{n}) = 4n - 9$</tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\widehat{ec}_{3}^{1}(S_{n}) = 6n - 15$</tex-math></inline-formula> when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$n \ge 6$</tex-math></inline-formula>, establishing the tight diagnosability bounds for this fundamental network topology. To enable practical implementation, we design a Trial System-based Fault Diagnosis Algorithm (TSFD) that features adaptive syndrome verification and parallel fault localization mechanisms. Extensive simulations demonstrate the accuracy of 98.99% fault detection with linear-time complexity <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$O(Nd)$</tex-math></inline-formula> in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i>-dimensional star networks. This work advances network reliability theory by introducing a multi-feature diagnosability measure for system-level diagnosis and developing an efficient diagnosis algorithm validated through large-scale network emulation.

State-of-the-art large data set high-precision sorting algorithms typically use hardware-accelerated radix sort. Advances in Dynamic Random Access Memory, Flash and High Bandwidth Memory (HBM) have enabled faster bandwidth intensive merge operations, where distribution-dependent data pre-processing techniques such as stochastic sampling bucketing offer alternatives impacted by increased data passes and vulnerability to data skew. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">This work addresses these limitations by introducing a compressed radix-sorting scheme for high-precision keys. Whereas radix sort histograms grow exponentially with precision, FractalSort guarantees bounded histogram size through the novel compression scheme which translates into smaller sorting circuits and reduced memory usage. Another key contribution is the novel optimized merge algorithm, which eliminates the need for data pre-processing and bucketing leading to higher bandwidth efficiency and reduced algorithm complexity. Using a tree-based recursive sorting architecture for space efficiency and low latency, the algorithm achieves fast sorting that exceeds the state-of-the-art on the CPU, FPGA, and GPU by 6x, 2.5x, and 3x bandwidth-adjusted throughput on 4GB to 2TB data sets. FractalSort is implemented on Xilinx Virtex UltraScale+ FPGA empirically demonstrating on-chip sorting at 20 Tb/s capable of memory-to-memory sorting of 32-bit keys at 3.2Tb/s using HBM.

This paper explores learnings from first-generation Compute Express Link (CXL) memory expansion to accelerate CXL’s journey to broad, robust use. While broad adoption will be a long journey similar to that of RDMA, we argue that the first step—CXL.mem expansion—is viable on today’s hardware. Through an end-to-end analysis, we revisit common showstoppers: we decompose memory access latency and show that CPU and DRAM internals, rather than the CXL protocol, dominate latency and variability, and we demonstrate how system slack absorbs link error rates above nominal specifications. Along the way, we distill practical guidance on device validation, monitoring, failure modes, security, and multi-tenant interference, and we outline a pragmatic adoption pathway: solidify robust expansion first, prototype micro-pooling next, and move to selective sharing as the ecosystem matures.

With the rapid advancement of big data processing and artificial intelligence (AI), data center networks (DCNs) must deliver more efficient resource management and data transmission mechanisms. Unfortunately, due to the significant differences in bandwidth requirements, transmission patterns, and temporal characteristics across various traffic types in DCNs (such as short flows, long flows, and bursty flows), traditional buffer allocation strategies fail to adapt flexibly to these disparities. In this paper, we propose Enhanced Buffer Management (EBM), a novel buffer-sharing scheme designed for scenarios that require higher performance from DCNs. Unlike prior approaches, EBM employs a multi-level flow identification and adaptive threshold adjustment mechanism to enhance the flexibility and efficiency of buffer management under varying traffic conditions. Specifically, EBM first performs coarse-grained and fine-grained classification of traffic based on packet size, inter-arrival interval, and other flow characteristics. It then applies an improved threshold computation function to allocate buffer space differentially across traffic classes while maintaining allocation smoothness. Our evaluation results demonstrate that EBM significantly improves performance under realistic workloads. For instance, it reduces the 99th percentile Flow Completion Time (FCT) slowdown by 32.7% for short flows in the web-search workload and by 45.1% for incast flows in the hadoop workload, all without sacrificing overall throughput.