In the domain of Photovoltaic (PV) power generation, the occurrence of hotspot phenomena is prevalent due to various factors, including cell mismatches within strings, shading, and mechanical damage. These hotspots are mitigated through the implementation of Bypass Diodes (BD). Innovative methodologies for hotspot mitigation integrate an additional active switch in series with the substring, in conjunction with the BD. This paper delineates a methodology designed to enhance these techniques by incorporating series and pull-down resistance within the gate circuit. Furthermore, it introduces a novel Complementary Switching Hotspot Mitigation (CSHM) circuit, which utilizes n-MOSFET and p-MOSFET components in series with the substring and within the bypass branch, respectively. The complementary switching performance is evaluated prior to constructing the CSHM module for experimentation. A comprehensive series of experiments has been executed on a 50-watt panel. A comparative analysis with conventional passive methods and prior techniques reveals a reduction in temperature in the shaded cell and an increase in output power. Moreover, the CSHM approach is practical, scalable, straightforward, and compatible with existing PV systems, thereby offering a resilient and effective solution for real-time hotspot mitigation.

This study investigates the degradation behaviors of two commercially available trench SiC MOSFETs with asymmetric trench gate and double trench gate under high gate voltage stress (both positive and negative). Experimental results reveal that the two gate structures exhibit markedly different degradation behaviors and temperature-dependent degradation responses after high gate voltage stress. Under high gate voltage stress, the double trench structure exhibits degradation behaviors analogous to conventional PBTI/NBTI phenomena, with enhanced degradation rates under negative gate voltage stress and temperature acceleration. In contrast, the asymmetric trench structure shows better reliability under equivalent stress conditions, particularly demonstrating negligible threshold voltage shift under negative bias. Temperature-dependent analysis revealed hole trapping at oxide layer dominates the asymmetric trench degradation process under positive bias, with anomalous threshold voltage reduction observed at high temperatures. Based on these findings, possible degradation mechanisms have been discussed and validated through C-V measurement. This work provides the detailed comparison of degradation behaviors between different gate structures under high gate voltage stress, offering valuable insights into the relationship between structural design and degradation mechanisms, which are critical for high-stress operational applications.

This paper presents a Semi-empirical Reliability Model for Hot-Carrier Degradation (HCD) in FinFET LDMOS devices. Unlike planar LDMOS, FinFET LDMOS exhibits non-saturating HCD over prolonged operation, due to its distinct three-dimensional geometry, which affects electric field distribution and carrier transport mechanisms. Traditional degradation models, such as the time slope exponent and bond dissociation (BD) approaches do not adequately capture this unique degradation due to the 3D structural complexities of FinFET LDMOS. To address this limitation, an enhanced model to account for HCD in FinFET LDMOS is introduced in this paper, significantly improving predictive accuracy for device lifetime. Hot-carrier Degradation for FinFET LDMOS is also characterized with variation in drain to source stress bias and number of fins (NFIN). When all other design parameters remain same, HCD increases with an increase in the drain-to-source stress voltage and reduces with an increase in the number of fins (NFIN).

Thermal annealing of radiation-induced degradation, especially at lower temperatures, requires an impractically long duration. This study investigates the efficacy of room-temperature electron wind force (EWF) annealing as a post-irradiation recovery treatment. Cascode GaN high-electron-mobility transistors (HEMTs) were exposed to gamma radiation doses of up to 10 Mrad.approximately 10 times higher than the average reported in the literature.resulting in significant degradation of their output and transfer characteristics. Our non-thermal annealing process appreciably mitigated radiation-induced damage within minutes. In contrast, similar studies in the literature required orders of magnitude more time and/or higher temperatures, even for lower doses (.500 Krad). These findings highlight the potential of EWF annealing as an in-operando treatment to enhance the resilience of GaN devices in radiation-intensive environments.

In this study, the effects of proton irradiation on the single event burnout (SEB) of p-gate AlGaN/GaN high-electron-mobility transistors (HEMTs) were investigated. SEB experiments were conducted using a femtosecond pulsed laser facility and a heavy ion accelerator, whereas proton irradiation was performed at the Proton Radiation Effects Facility (PREF). Additionally, a significant reduction in the threshold voltage for SEB (VSEB) is observed after 30 MeV proton irradiation at a fluence of 2E11 cm-2. Further analysis using deep-level transient spectroscopy (DLTS) reveals that the original electron trap E0 (Ec–0.81 eV) evolves into an electron trap E2 (Ec–0.72 eV) and a hole trap H2 (Ev+0.88 eV) after irradiation. This reduction in VSEB is due to significant positive charge accumulation resulting from the H2. Furthermore, the safe operating areas (SOAs) for SEB effects in GaN HEMTs, both before and after proton irradiation, are given. During SOA analysis, a reduction in VSEB under more negative gate voltage after proton irradiation is observed, attributed to increased hole trapping by proton-induced trap H1 (Ev+1.00 eV) and residual E0 traps, which maintain a high electric field at the drain edge.

High-energy neutrons, alpha particles, photons, and heavy ions pose a significant threat to the operation and stability of SRAMs in aerospace applications. These particles can considerably corrupt data, particularly at lower technologies, causing node upsets. Conventional 6T SRAMS are not capable of operating in such conditions. Instead, radiation-hardened by design (RHBD) SRAMs are employed. Existing RHBD SRAM circuits are typically capable of tolerating single-node upsets and, to a limited extent dual-node upsets, but they are generally ineffective against comprehensive dual-node upsets. This paper introduces a novel 14-transistor (14T) RHBD SRAM implemented in 28 nm CMOS technology, which robustly mitigates SNUs as well as complete dual-node upsets (DNUs). The proposed 14T SRAM cell achieves a low leakage power of 1.65 nW per cell and exhibits a significantly enhanced read static noise margin (RSNM). Compared to other existing RHBD designs, our proposal shows the least write access time of 0.17 ns, reduced power consumption with dynamic energy at 72 fJ/cell and 100% bit recovery even in DNUs. Subsequent Monte Carlo and post-layout simulations confirm that the proposed SRAM design is sufficiently stable and robust in high radiation regions, making it suitable for space applications.

The high-voltage operation of GaN power high-electron mobility transistors (HEMTs) is primarily limited by electric field crowding near the gate field plates, which, over time, can degrade the dielectric properties of the passivation layer or gate insulators and compromise device reliability. Therefore, understanding the different breakdown mecha-nisms—X;their causes and locations—X;is essential for optimizing device design and improving off-state performance. Previous studies have primarily focused on device reliability in GaN HEMTs with doped buffer layers. By contrast, this study fo-cuses on the effects of prolonged off-state stress in Metal-Insu-lator-Semiconductor (MIS)-gated GaN HEMT with an Al-GaN/GaN/AlN heterostructure design without a buffer layer. The devices are investigated using electrical characteriza-tion, nanoscale structural/chemical analysis (SEM, TEM, EDS). Additionally, technology computer-aided design (TCAD) simulations are employed to describe the breakdown process by studying the electric field and charge distribution in the dielectrics. Based on the structural/chemical analysis, as well as the TCAD simulation results, it is suggested that the formation of a vertical percolation path in the SiNx passivation layer underneath the field plate edge initiates the destructive breakdown process.

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising alternative to existing memory technologies. However, STT-MRAM faces reliability challenges, primarily due to stochastic switching characteristics, process variation, and manufacturing defects. Furthermore, these reliability challenges worsen as technology scales down due to the increasing dominance of interconnect parasitic resistive-capacitive (RC) effects. We propose an efficient location-aware error-correcting code (ECC)-based strategy for mitigating the impact of interconnect parasitics on STT-MRAM bit-cell reliability. By applying a non-uniform error correction mechanism across different memory zones, our approach increases correction strength with distance from the driver. The proposed approach avoids the need for uniformly strong error correction across the whole memory zone, thereby reducing ECC parity bit memory overhead while improving the reliability in the vulnerable memory zone. Furthermore, the proposed strategy has a negligible effect on system performance, as measured by instructions per cycle (IPC).

High-temperature dc and ac capacitance dispersion analysis of the double-p gate AlGaN/GaN high electron mobility transistor (HEMT) is simulated to analyze the trapping effects. Self-heating phenomena in electronic devices degrade both performance and lifetime. Self-heating effects (SHE) lead to a rise in channel temperature, which directly impacts the bandgap (EG), mobility of the electrons (μ e), electron saturation velocity (Vsat), threshold voltage (VTH), breakdown voltage (VBD), transconductance (gm), drain saturation current (IDS), output power (Pout) as well as memory effects and noise performance. To mitigate self-heating effects, a new double-π gate HEMT is designed with the gate stem divided into three pillars. This structure redistributes the electric field and reduces phonon scattering. Notably, the device current collapse (CC) percentage drastically decreased when operated at high temperature. Capacitance dispersion is simulated using 2-D TCAD across ambient temperatures ranging from 253∘ K to 1098∘ K. Simulation results showed minimal hot electron generation and trapping effects at extreme temperatures. A slight kink effect is observed at temperatures above 773∘ K for gate stem distances greater than 150 nm.