A novel dual-mode dual trench MOSFET (DDT-MOSFET) featuring shorted P-doping field plate (PFP) and N-doping field plate (NFP) is proposed. A parasitic depletion region capacitor and a parasitic MOSFET are introduced in the self-adjustable field plate (SFP). During turn-on, the DDT-MOSFET is in the split gate trench (SGT) mode with an electron inversion layer in the PFP, achieving low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm { gd}}$ </tex-math></inline-formula>. During turn-off, the DDT-MOSFET is in the insulator pillar superjunction (I-SJ) mode with depleted PFP, achieving low electromagnetic interference (EMI) noise and high breakdown voltage (BV). Mode conversion is realized by the introduction of the SFP. By TCAD simulation, during turn-off, the proposed structure exhibits 33.9% improvement in BV, 42.8% reduction in maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$dI_{\mathrm { D}}$ </tex-math></inline-formula>/dt and 44.1% reduction in overshoot voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(V_{\mathrm { O}})$ </tex-math></inline-formula> with same <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E_{\mathrm { off}}$ </tex-math></inline-formula>, reducing EMI noise and improving dynamic avalanche robustness without deterioration of other electrical characteristics.

As the electromigration (EM) reliability margin reduces rapidly with scaling, novel approaches for EM-compliance checks are being intensively sought to enable more accurate and less conservative analyses. Currently, chip-level EM reliability is assessed based on the failure probability of individual lines and vias in the BEOL stack, overlooking potential redundant connections that could still ensure circuit operation despite isolated failures. This is particularly relevant for the power delivery network (PDN), which is redundant by definition due to its regular mesh structure. In this work, we leverage a new approach to perform EM-compliance checks that relies on considering the PDN as a matrix of identical network units-cells, henceforth referred to as tiles, and using them to compute the overall failure risk. As opposed to conventional methods, our approach captures the impact of redundancy within each individual PDN tile, thereby providing less conservative reliability estimations. After reviewing standard methods for EM-compliance checks, namely limit-based and statistical EM budgeting (SEB), we quantify the additional reliability margin provided by our PDN-tile approach. For our analysis, we considered a PDN featuring three different metallization schemes for Dual Damascene (DD) Cu/Low-k interconnects utilizing SiCN capping, Cobalt (Co) capping with and without Ruthenium (Ru) via prefill. Using the standard SEB method indicated that Co capping and Co capping + Ru Via Prefill lead to reductions in EM failure risk by 5 and 7 orders of magnitude, respectively, compared to SiCN capping. The new approach was implemented for the first metallization with SiCN capping. At 10 years lifetime, our PDN-tile approach foresees a failure probability which is 3 orders of magnitude smaller than the SEB approach. At an equivalent failure probability of 100ppm and the same target lifetime of 10 years, the current of standard cells can be increased by 2.8-fold, giving designers more margin to improve chip performances.

Transformers have achieved remarkable success in diverse fields such as Natural Language Processing (NLP) and computer vision (CV). For pre-trained Transformer models involving text processing, embedding representations are important parameters, incurring a large volume of memory. Soft errors on embedding vectors can lead to incorrect inputs to Transformers, and if not corrected in time, accumulated errors may produce undesirable outcomes. This paper considers the dependability of text related Transformer models to accumulated errors on embedding parameters and takes three typical models in different applications as case studies: BERT based sentence emotion classification, T5 based text summarization, and CLIP based image classification. We first evaluate the dependability of the three models by injecting bit errors on embedding parameters; only errors on a few critical bits affect model performance. Based on this finding, we first propose an efficient selective protection for embedding parameters with small values, and then through scaling, we extend the scheme for models with large embedding parameters. Extensive simulation results show that the proposed protection scheme can effectively remove the impact of soft errors on task performance. In particular, the complexity overhead of the proposed scheme is negligible, and the additional memory overhead as encountered in the SEC scheme is avoided.

The total ionizing dose (TID) responses of 0.35 lm and 0.13 lm SiGe HBTs at liquid-nitrogen temperature (78 K) were investigated using 10 keV X-rays. For the first time, we compared the annealing behaviors of SiGe HBTs irradiated at 78 K and room temperature (297 K). The results reconfirm that SiGe HBTs have superior TID tolerance up to Mrad(Si) levels, and the current gain degradation of DUTs irradiated at 78 K is much less than those irradiated at 297 K. However, the 0.35μ m SiGe HBTs irradiated at 78 K show further degradation after room temperature annealing (RTA) due to the thermal activation of oxide charge migration and the long-term buildup of interface traps. The 0.13 lm SiGe HBTs irradiated at 78 K show minor change after RTA, which can be attributed to the competition between interface trap creation and annealing.

With the scaling of integrated circuit technologies, charge-sharing effects induced by single-event transient (SET) have become a critical reliability concern in radiation environments. However, conventional circuit-level SET simulation methodologies fail to account for charge-sharing mechanisms among adjacent devices. This work proposes a physics-aware simulation framework combining technology computer-aided design (TCAD) device simulations and circuit-level modeling to address this limitation. The methodology involves extracting transient current waveform parameters through 3D TCAD simulations under varied ion strike locations. Spatially-dependent behavioral models are then developed via multivariate regression of these parameters, which are subsequently integrated into bias-dependent SET analytical models. To enable circuit-level analysis, built-in current sources characterized by the developed models are inserted at sensitive nodes during layout-aware simulations. The proposed approach is validated through comparative analysis between TCAD mixed-mode simulations and circuit-level predictions in a 12-nm FinFET test structure, demonstrating smaller deviation in critical SET metrics. Compared to existing methods, this co-simulation strategy incorporates both charge-sharing effects and bias voltage dependencies while maintaining computational efficiency. The implemented framework enables early-stage evaluation of radiation-induced soft errors during physical design phases, providing critical insights for radiation-hardened-by-design strategies in advanced process nodes.

Quantifying activation energy (Ea) is essential for evaluating the thermal reliability of NAND flash memory technologies. Conventional approaches rely on threshold voltage (Vt) shift measurements under thermal stress, which are often inaccessible in Commercial Off-The-Shelf (COTS) NAND devices. In this work, we present a digital probing method to estimate activation energy using fail bit counts (λFBC), enabling reliability evaluation without requiring direct V. access. The proposed technique tracks bit-flip events caused by charge loss or injection at elevated temperatures (40∘C to 120 ∘C) and computes the median fail bit count (VFBC) over time. Using the Arrhenius relationship, we extract activation energies of 1.09 eV and 0.76 eV for 2D and 3D multi-level cell (MLC) NAND flash memory, respectively. The results highlight the architectural differences in degradation behavior and demonstrate the efficacy of.FBC as a digital reliability metric. Comparative analysis with existing threshold voltage-based methods validates the accuracy of the proposed technique. This work establishes a non-invasive and scalable method for activation energy extraction, facilitating comprehensive reliability characterization across modern NAND flash technologies.

Metallized film capacitors (MFCs) are valued for their ability to withstand high-electric-fields, yet they face short-term failure risks when subjected to overvoltage-induced self-healing (SH). This paper presents a monitoring method designed to address the challenges posed by multiple instances of SH in pulsed power applications. Traditional capacitance estimation using sampled current during SH is hindered by the significant arc current. To address this, the study explores the dynamic interplay between sampling current, arc current, and MFC current throughout the SH process. The introduction of Kalman filtering effectively mitigates the impact of noise signals on capacitance monitoring during the short-term cumulative discharge process of SH. Experimental and simulation results attest to the efficiency of the proposed approach, demonstrating an estimation error of less than 1%. Furthermore, a thorough structural analysis of MFCs demonstrates that the proposed method can effectively identify the transition from isolated, safe SH behavior to clustered, disruptive SH events, thereby enabling timely intervention to prevent severe damage.