Stacked dynamic random access memory (DRAM) technology has garnered considerable attention as a means to continue the relentless pursuit of scaling. In this context, we have developed a five-layer horizontal cell with vertical word line (WL) and pillar capacitor to realize a stacked DRAM architecture. This design boasts an excellent combination of high <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small>-state current ratio (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}$</tex-math> </inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {off}}\text {)}$</tex-math> </inline-formula> of ~1E8, a steep subthreshold slope (SS) of ~93 mV/dec and a moderate threshold voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{t}\text {)}$</tex-math> </inline-formula> of 0.76 V. A novel process integration scheme incorporating boron silicate glass (BSG)/phosphorus silicate glass (PSG) capping doping, double gate formation, channel thickness optimization, and device electrical engineering considerations are presented and discussed. Moreover, we have also explored the feasibility of fabricating a 64-layer structure through the development of critical unit processes. This study suggests a promising approach using multilayer horizontal cells (MHCs) to further advance the scaling of DRAM technology.

Hole trap profiles in the charge trap layer (CTL) of 3-D <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nand</small> flash memory are characterized using a newly proposed bias-induced hole trap extraction (BITE) technique. At 400 K, the appropriate emission bias (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">emit</sub>) regimes are determined by analyzing emission rates to ensure that the Poole–Frenkel (PF) emission, followed by band-to-band (BB) tunneling, constitutes the dominant hole emission mechanisms. The hole trap distribution is quantitatively extracted from time-dependent charge loss characteristics using a retention model formulated in cylindrical coordinates. The resulting trap profile shows a Gaussian-like distribution with the peak density at 4.3×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–3</sup> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot$</tex-math> </inline-formula> eV<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–1</sup> at 0.87 eV. As the measurement temperature decreases, the trap density at deeper energy levels declines, which is attributed to the increasing contribution of the trap-to-band (TB) emission mechanism.

The Ga<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub>-based memristors, fabricated via electron beam evaporation (EBE), exhibit both volatile and nonvolatile resistive switching behaviors. The nonvolatile Ga<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub>-based memristors exhibit remarkable resistive switching properties, featuring outstanding cyclic stability, a substantial switching window (>100), and notably low SET/RESET voltages. The observed dual switching modes are attributed to filamentary conduction driven by metallic Cu filaments assisted by oxygen vacancies. The studied Ga<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub>-based devices demonstrate both electrically and optically tunable synaptic functionalities, including paired-pulse facilitation (PPF), spike-rate-dependent plasticity (SRDP), spike-timing-dependent plasticity (STDP), potentiation and depression behaviors, as well as light-induced memory characteristics and learning-forgetting capabilities. Intriguingly, high recognition precision of 89.14% on Fashion-MNIST and 97.84% on modified National Institute of Standards and Technology database (MNIST) indicates that wide bandgap semiconductor Ga<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub>-based memristors hold immense potential for advancing future neuromorphic computing.

The impact of the sheet carrier density, the barrier design, the introduction of AlN interlayer, and the substrate temperature on the saturation velocity in ungated GaN-based heterostructures were measured over multiple process runs. In addition, gate-transit delays were extracted on 150-nm transistors to verify the extracted data on a transistor level. Empirical models were derived for the saturation and effective carrier velocity in dependence on all parameters to allow for a simple estimation of the current density for a wide majority of GaN-based heterostructures. In addition, an empirical model for the temperature dependence (up to 400 K substrate temperature) is provided, allowing for a direct estimation of the intrinsic saturation velocity decrease for substrate temperatures close to the operation condition of high-power amplifiers.

Multifunctional optoelectronic logic gates (OELGs) hold significant promise for high-speed and high-security data processing applications. In this work, a Pt/Ga<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub>/GaN heterojunction device is fabricated to implement multifunctional logic operations by leveraging a bias- and wavelength-selective competitive current mechanism. At 0-V bias, the device exhibits a significant pyro-photoelectric coupling effect, which markedly enhances the transient photoresponse to both 254- and 365-nm illumination. Under forward bias (0.55–2 V), 365-nm illumination simultaneously induces competing photogenerated current and recombination current, resulting in a net photocurrent under 254- and 365-nm co-illumination that is lower than that under 254-nm illumination alone. In contrast, under reverse bias, the photocurrent under dual illumination exceeds that under single-wavelength illumination. The distinct photocurrent magnitude relationships under forward and reverse bias, originating from this wavelength- and bias-dependent competition mechanism, enable four reconfigurable logic operations—<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">not</small>, <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">or</small>, <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nor</small>, and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nand</small>—within a single Pt/Ga<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub>/GaN device.

With the increasing connection of high-proportion renewable energy into power grids, the grid-forming converter technologies have gained significant attention due to their active support capability. When the power system experiences disturbances causing voltage sags of varying degrees, the overcurrent problems of insulated-gate bipolar transistor (IGBT) in the grid-forming converters threaten the safety and stability of the power system. To enhance the overload withstand capability of IGBT, many studies about optimization in terms of cell structure, packaging structure, and control strategy have been conducted. The state-of-the-art cell structure optimization of IGBT with an improved tradeoff relationship between <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\textsc{on}}\text {)}$</tex-math> </inline-formula> and turn-off energy loss (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\textsc{off}}\text {)}$</tex-math> </inline-formula> to lower power loss is reviewed. The progress of various technologies is discussed and analyzed in detail. The principles, implementation methods, and limitations of the technologies are summarized in the end.

This article presents a comprehensive framework for high-efficiency in-memory computing based on a physics-driven compact model for 3-bit interface-type self-rectifying resistive random access memory (SR-RRAM). The model, grounded in electric-field-driven alkali ion migration and the Schottky barrier lowering effect, accurately captures the multilevel switching behavior, demonstrating exceptional agreement with experimental data (0.02% dc error and 2.75% ac error). Benchmarking against established filamentary models reveals a fivefold improvement in fitting accuracy [1.12% root mean square error (RMSE)], validating its suitability for interface-type devices. Leveraging this model, we demonstrate a vertically integrated co-design methodology for a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$64\times 64$</tex-math> </inline-formula> vector-matrix multiplication (VMM) accelerator. We introduce a novel bias scheme exploiting the device’s intrinsic nanobattery effect (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {EMF}}$</tex-math> </inline-formula>), which suppresses sneak current error to 0.012%. Furthermore, a SPECTER-validated shared analog-to-digital converter (ADC) architecture is implemented, reducing the total system area by 52.5% and energy consumption by 77.0%. The resulting system achieves a peak energy efficiency of 22.05 TOPS/W (180 nm node) and maintains a high VMM computational accuracy of 97.1% (MNIST full test set), paving the way for robust and efficient neuromorphic hardware.

Two Trench field-stop (FS) 1200 V/15 A carrier-storage semi-super-junction insulated gate bipolar transistors (CS-SemiSJBTs) are experimentally presented for the first time, whose SJ-pillar both are fabricated in the Multi-Epi process with thickness of 45 μm, and its pitch of cathode gate is 6 μm. Two commercial Trench/micro-pattern-trench (MPT) FS N-drift IGBT (NDBTs) are selected as benchmarks. Wafer thickness of fabricated CS-SemiSJBTs is 101 μm, along with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V} _{\text {on}}$</tex-math> </inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{C} _{\text {res}}$</tex-math> </inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{t} _{\mathrm{d},\text {on}}$</tex-math> </inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{t} _{\mathrm{r}}$</tex-math> </inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{t} _{{\mathrm{d}},\text {off}}$</tex-math> </inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{t}_{\mathrm{f}}$</tex-math> </inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{E} _{\text {on}}$</tex-math> </inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{E} _{\text {off}}$</tex-math> </inline-formula>, all are reduced from referenced NDBTs under the effect of SemiSJ-pillar. According to measurement results, one of the CS-SemiSJBT has the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t} _{\text {sc}}$</tex-math> </inline-formula> of 4.7 μs similar to H6, and its FOM is 1.4 times as H6; another CS-SemiSJBT has <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t} _{\text {sc}}$</tex-math> </inline-formula> of 15 μs similar to S7, and its FOM is 1.3 times as S7.