This work first reveals the robustness and degradation mechanisms of a 200-V p-GaN high-electron-mobility transistor (HEMT) under the load-dump stress with the gate biased at different conditions. The gate conditions involved in this work include the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small>-state (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {GS}} =0$</tex-math> </inline-formula> V), semi-<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {GS}} =1.6$</tex-math> </inline-formula> V), and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {GS}} =6$</tex-math> </inline-formula> V). The experimental results indicate that the device has the weakest tolerance to the load-dump stress in the semi-<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state compared with the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small>- and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-states. Specifically, in the semi-<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state, the device immediately failed when the load-dump stress was increased to 100 V. While under the other two conditions, the device still works even when the load-dump stress was increased to 150 V. This phenomenon is closely related to the high local current concentration phenomenon, companying with the high electric field peak at the gate region for the device in the semi-<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state. In addition, the devices’ threshold voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}\text {)}$</tex-math> </inline-formula> and drain current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {DS}}\text {)}$</tex-math> </inline-formula> show different drift degrees after applying the load-dump stress under different gate biases. Among them, it is worth noting that the device exhibits the most significant degradation phenomenon after the load-dump stress is applied in the semi-<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state.

HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>-based ferroelectric field-effect transistors (FeFETs) are promising contenders for nonvolatile memory (NVM) devices due to their CMOS compatibility and scalability. However, conventional metal–ferroelectric (FE)–interfacial layer (IL)–silicon (MFIS) structures often suffer from a limited memory window (MW) and poor program/erase (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P$</tex-math> </inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E$</tex-math> </inline-formula>) cycling endurance due to the unfavorable gate potential distribution across the gate-stack. To address these challenges, we propose a novel vertical FE–metal field-effect transistor (V-FeMFET), incorporating a metal–FE–metal–IL–silicon (MFMIS) gate-stack in a vertical channel-all-around (CAA) configuration. By integrating a metal–FE–metal (MFM) capacitor above a cylindrical metal–IL–silicon (MIS) capacitor, the architecture enables an intrinsically small area ratio (AR) between the FE area (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${A} _{\text {FE}}$</tex-math> </inline-formula>) and the channel area (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${A} _{\text {MIS}}$</tex-math> </inline-formula>) without sacrificing the device footprint. The memory characteristics of the proposed V-FeMFET were comprehensively analyzed through precisely calibrated technology computer-aided design (TCAD) simulation. By optimizing the AR through spacer thickness engineering, a wide MW of 3.0V was achieved under low-voltage, high-speed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P$</tex-math> </inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E$</tex-math> </inline-formula> pulses (±2V/100ns). Furthermore, the device exhibits a reduced electric field across the IL, which potentially improves the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P$</tex-math> </inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E$</tex-math> </inline-formula> cycling endurance. A rigorous analysis combining load-line analysis and capacitance ratio (CR) evaluations clarified the mechanism behind the MW expansion. These results demonstrate that the V-FeMFET offers significant advantages in terms of MW, reliability, scalability, and back-end-of-line (BEOL) compatibility, positioning it as a promising solution for versatile NVM applications.

Accurate knowledge of phonon transport lengths is essential for predicting size-dependent thermal conductivity in modern semiconductor devices, yet existing “average” phonon mean free path (MFP) definitions are often crude and inconsistent. This work provides the first-principles calculation of the effective MFP, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Lambda _{\text {eff}}$</tex-math> </inline-formula>, obtained directly from thickness-dependent thermal conductivity of 17 modern semiconductors including Si, Ge, diamond, silicon carbide (SiC), GaN, AlN, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $</tex-math> </inline-formula>-Ga<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub>, and others. We compare <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Lambda _{\text {eff}}$</tex-math> </inline-formula> with three commonly used MFP metrics, conventional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Lambda _{\text {conv}}$</tex-math> </inline-formula>, midpoint <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Lambda _{\text {mid}}$</tex-math> </inline-formula>, and weighted-average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Lambda _{\text {ave}}$</tex-math> </inline-formula>. Our results show that <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Lambda _{\text {conv}}$</tex-math> </inline-formula> severely underestimates phonon transport lengths, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Lambda _{\text {mid}}$</tex-math> </inline-formula> provides only a partial approximation, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Lambda _{\text {ave}}$</tex-math> </inline-formula> is strongly biased toward long-MFP phonons. In contrast, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Lambda _{\text {eff}}$</tex-math> </inline-formula> reliably predicts when a material transitions from bulk-like to ballistic or quasiballistic conduction, making it the most physically meaningful descriptor for device-scale modeling. We also introduce a “normalized effective MFP” that quantifies transport length per unit heat carried, and a two-MFP model that captures both short- and long-MFP phonon channels while closely matching first-principles results. The tabulated <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Lambda _{\text {eff}}$</tex-math> </inline-formula> values and the proposed models provide compact, experimentally accessible tools for thermal design in transistors, RF and power electronics, optoelectronics, quantum devices, and other nanoscale semiconductor technologies.

A novel trench insulated gate bipolar transistor (IGBT) with shielding hole path (SHP) is proposed and experimentally demonstrated. During turn-on, the SHP shields the gate–collector coupling and provides a hole path (HP) near the main current path. A hole barrier is introduced near the gate trench to shield hole accumulation and form a hole depletion region. A hole well is introduced near the split-gate (SG) trench to enhance hole extraction through the SHP. Consequently, the displacement current that charges the gate electrode is effectively suppressed through the reduction of both the effective <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {GC}}$</tex-math> </inline-formula> for holes and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit {dV}_{\text {acc}}$</tex-math> </inline-formula>/<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</i>. The experimental results show that, compared to the floating P-Region IGBT (FP-IGBT), the SHP-IGBT achieves a 49.0% lower <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit {dI}_{\text {C}}$</tex-math> </inline-formula> /<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</i> at the same <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {G}}$</tex-math> </inline-formula> and a 54.7% lower <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit {dV}_{\text {KA}}$</tex-math> </inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit {dt}_{\max }$</tex-math> </inline-formula> at the same <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {on}}$</tex-math> </inline-formula>, reducing electromagnetic interference (EMI) noise without degrading other electrical parameters. In addition, a refined displacement current model incorporating the effective <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {GC}}$</tex-math> </inline-formula> for holes is proposed.

We study the computing capability of ferroelectric field-effect transistor (FeFET) reservoir computing (RC) systems under bipolar stress which can potentially degrade the MOS interface of FeFET. When pulses are fed to the FeFET over a long term, there is a change in the FeFET output current dynamics due to MOS interface degradation, affecting the computing capability of FeFET RC systems. To mitigate the change in FeFET output currents, precycling is effective to sustain the computing capability of the FeFET RC system because it slows down the change of dynamics in the FeFET over stress cycles. Sequential retraining is another effective method, as the updated weights absorb the change of dynamics in the FeFET after the interface degradation, resulting in a stable computing capability for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${10}^{{7}}$</tex-math> </inline-formula> input pulses. We show that the FeFET RC system remains stable regardless of interface degradation as long as there is still sufficient polarization dynamics. The difference between memory window (MW) and RC capability, the former eventually disappearing after bipolar stress, the latter remaining stable by precycling or the sequential retraining, is because they reflect different physical properties of FeFETs—MW reflects the final device state after applying a gate voltage, while RC utilizes the device dynamics during a gate voltage application.

Accurate junction temperature prediction in multichip insulated gate bipolar transistor (IGBT) modules is paramount for ensuring the reliability and efficiency of power electronic systems. Given the high integration density and intricate thermal coupling among multiple chips, developing an efficient method for junction temperature estimation is essential for IGBT power modules. This article presents a novel digital twin-based method for accurately monitoring junction temperature in multichip power modules. A digital twin modeling framework of IGBT testing is first presented. Subsequently, the current-sharing behavior in multichip power modules is analyzed and systematically modeled. Power loss calculations based on the current balancing are then performed, complemented by finite element simulations to derive the temperature distribution and heat-dissipation characteristics of the module. Leveraging this foundation, a convolutional neural network (CNN)-enhanced digital twin approach is proposed to achieve real-time temperature prediction. The effectiveness and accuracy of the proposed method are rigorously validated through a double-pulse test (DPT) platform and reactive aging experiments. The results demonstrate that this framework offers a highly efficient solution for real-time junction temperature monitoring and thermal management in multichip IGBT modules.

This work investigates the thermal characteristics of gallium nitride (GaN) high-electron mobility transistors (HEMTs) for power applications. Exemplarily, a 650-V class HEMT is analyzed by different thermal characterization methods such as transient <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$</tex-math> </inline-formula>–<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$</tex-math> </inline-formula> measurements, infrared (IR) microscopy, and simulations, presenting a comprehensive insight into the thermal behavior. A new electrothermal model function is derived for the extraction of thermal parameters by transient <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$</tex-math> </inline-formula>–<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$</tex-math> </inline-formula> measurements, and it is not limited to the linear region of the output characteristic, as a model presented in previous work, but also applicable in the saturation region. Fifth-order Foster model parameters are extracted for different operating points in linear and saturation regions. For verification and better understanding, the measurements are also performed by IR microscopy at same operating points enabling the characterization of the device’s surface temperature distribution. Two new analytical models allow the interpretation of the temperature distribution and are used as fit formulas for extracting the thermal parameters found by IR microscopy. Finally, the research includes an investigation using technology computer-aided design (TCAD) simulation, followed by a thermal 3-D finite element simulation. The results allow a deeper understanding of the electrothermal behavior of GaN power HEMTs at various operating points.

We report a voltage-induced resistance drop with power-law behavior in silver nanoparticle composites operated near the conductor-to-insulator percolation threshold (PT). Upon prolonged electrical pulsing, resistance decreases in a time-dependent power-law fashion, indicating dynamic plasticity in the composite’s internal network. We identify a threshold voltage (~<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {5} {\,}\text {V}$</tex-math> </inline-formula>) required to trigger this effect and demonstrate partial recovery via thermal annealing at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${80} ^{~\circ }\text {C}$</tex-math> </inline-formula>. This behavior is reminiscent of spike-timing-dependent plasticity (STDP), drawing parallels to synaptic learning dynamics observed in neuromorphic architectures. To explain these dynamics, we develop a percolation-based resistor network model incorporating STDP-like updates. Our results highlight tunable resistive behavior in silver nanoparticle composites at the edge of percolation and bridge percolation physics with bio-inspired learning mechanisms.

In this work, a threshold coupling (TC) AlGaN/GaN high-electron-mobility transistor (HEMT) incorporating a composition-modulated Al<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> _x </i>Ga<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\text {1-}{x}}$</tex-math> </inline-formula>N barrier (CM.TC HEMT) distinguished by 100 V high-linearity operation has been proposed. Al composition (Al%) was pertinently designed in the barrier to accomplish charge redistribution, thus mitigating electric field (E-field) crowding in the recessed part of a conventional TC structure (Con.TC HEMT) and addressing its diminished linearity effectiveness under high operating voltages. As a result of the epitaxial optimization, transconductance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${G}_{\text {m}}$</tex-math> </inline-formula>) roll-off with increased drain biases was suppressed, and the breakdown voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BK}}$</tex-math> </inline-formula>) was improved from 152 to 298 V. In 3.6 GHz large signal measurement with a drain voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$</tex-math> </inline-formula>) of 48 V, the CM.TC HEMT demonstrated comparable saturated output power density (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {sat}}$</tex-math> </inline-formula>) to the Con.TC HEMT, while achieving a 6% higher peak power-added efficiency (PAE) and a 3 dB improvement in output third-order intercept point (OIP3). 100 V single and two-tone evaluation further revealed a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {sat}}$</tex-math> </inline-formula> of 14.7 W/mm and an OIP3 of ~42.7 dBm for the CM.TC HEMT. The reported device extends the linearity benefits originally enjoyed by moderate voltages to an elevated scenario, which is promising for serving power amplifiers (PAs) that require both high-linearity and high-voltage operation.

Modern ultraviolet (UV) detection applications require compact, high-performance detectors compatible with mass production. In this study, we present a silicon-on-insulator (SOI) monolithically integrated photodiode (PD)-MOSFET UV detector fabricated via a fully CMOS-compatible process, achieving exceptional responsivity and detectivity. The proposed detector integrates a cross-finger PD with a MOSFET by connecting the PD anode to the MOSFET gate. Thus, the PD detects UV illumination, and subsequently, the signal is amplified by the MOSFET. A systematic investigation of the top-silicon thickness and PD dimensions enables balancing the responsivity and UV selectivity. Under 260 nm illumination at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3~\mu $</tex-math> </inline-formula>W/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, the device attains a responsivity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.54\times 10^{{6}}$</tex-math> </inline-formula> A/W, an external quantum efficiency (EQE) of 1.21 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 10^{{9}}$</tex-math> </inline-formula>%, and a detectivity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.61\times 10^{{19}}$</tex-math> </inline-formula> Jones—over a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{7}}$</tex-math> </inline-formula>-fold improvement compared to a standalone PD. The measured rise and decay times are 11.8 and 29.5 ms, respectively, under <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5~\mu $</tex-math> </inline-formula>W/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> illumination. Sentaurus TCAD simulations show that these can be reduced to 0.46 and 0.62 ms through gate dimensions scaling and buried oxide (BOX) thickness modulation. Temperature-dependent measurements reveal the impact of elevated temperatures on device performance. The combination of high performance and CMOS compatibility makes this detector a promising candidate for UV detection applications such as UV imaging and communication.