Skyrmion racetrack memory (SK-RM) has become a promising memory medium in future computer systems, thanks to the exceptional access performance and storage density. Its unique features, such as the supports of parallel reads/writes and random inserts/deletes, create new opportunities to address the design challenges of existing data structures. In particular, directly storing a B-tree on SK-RM might result in occasional spikes in the latency when inserting a data item into the B-tree. The primary cause of the unstable performance is due to the inefficient node splitting procedure, in which nearly half of the data items of the overflowing node must be migrated to a new node. In this work, we present Skr-tree, a highly responsive variant of B-tree for general SK-RMs. To reduce the worst-case latency of data item insertion, Skr-tree comes with a novel node splitting strategy called remapping split, which modifies the node metadata to remap a part of the data items of an overflowing node to a new node. To accompany the remapping split strategy, Skr-tree is also equipped with a node rebalancing strategy which amortizes the data item migration to different data item insert operations and reduces the instantaneous latency of node splitting. To validate the performance benefits of Skr-tree, a series of analytical and experimental studies have been performed, and the results are quite encouraging.

Conventional synchronous federated learning (SFL) frameworks suffer from performance degradation in heterogeneous systems due to imbalanced local data size and diverse computing power on the client side. To address this problem, asynchronous FL (AFL) and semi-asynchronous FL have been proposed to recover the performance loss by allowing asynchronous aggregation. However, asynchronous aggregation incurs a new problem of inconsistency between local updates and global updates. Motivated by the issues of conventional SFL and AFL, we first propose a time-driven SFL (T-SFL) framework for heterogeneous systems. The core idea of T-SFL is that the server aggregates the models from different clients, each with varying numbers of iterations, at regular time intervals. To evaluate the learning performance of T-SFL, we provide an upper bound on the global loss function. Further, we optimize the aggregation weights to minimize the developed upper bound. Then, we develop a discriminative model selection (DMS) algorithm that removes local models from clients whose number of iterations falls below a predetermined threshold. In particular, this algorithm ensures that each client's aggregation weight accurately reflects its true contribution to the global model update, thereby improving the efficiency and robustness of the system. To validate the effectiveness of T-SFL with the DMS algorithm, we conduct extensive experiments using several popular datasets including MNIST, Cifar-10, Fashion-MNIST, and SVHN. The experimental results demonstrate that T-SFL with the DMS algorithm can reduce the latency of conventional SFL by 50%, while achieving an average 3% improvement in learning accuracy over state-of-the-art AFL algorithms.

Object Exploration and Mapping (OEM) is a novel embodied AI task that requires an agent to autonomously explore unknown environments, simultaneously detect and localize multiple objects, and construct a semantic object-level map. To solve this challenge, we propose a two-stage framework. First, a deep reinforcement learning-based OEM framework (DRL-OEM) is proposed to leverage auxiliary perception tasks and memory-augmented policy learning to guide efficient exploration. Second, we extend the DRL-OEM to Meta-OEM, where a meta-reinforcement learning framework is employed to enhance adaptation to unseen environments with a novel key-behavior-aware prioritized sampling strategy by reusing high-reward transitions. Extensive experiments conducted on customized AI2Thor scenes across diverse layouts and object configurations demonstrate that Meta-OEM significantly outperforms strong baselines, including DRL-OEM, PEARL, and MQL, achieving up to 2× higher success rates and faster convergence during adaptation. Visual and quantitative results confirm its superior object discovery coverage, pose estimation accuracy, and generalization capability in open-world scenarios.

Artificial-intelligence-powered edge devices are inspiring interest in always-on, intelligent, and self-powered visual perception systems. Due to the high energy cost of converting raw data and the limited computing and energy resources available, designing energy-efficient and low bandwidth CMOS vision sensors is vital as these emerging systems require continuous sensing and instant processing. This paper proposes a low-power integrated sensing and computing engine, namely <monospace>APRIS</monospace>, including a novel software/hardware co-design technique. This method provides a highly parallel analog multiplication and accumulation-in-pixel scheme, which realizes low-precision quantized weight neural networks to mitigate the overhead of analog-to-digital converters and analog buffers. Moreover, in order to reduce the size and power consumption, we propose the implementation of an approximate ADC in the readout circuit. Our system utilizes eight memory banks to increase computation parallelism, which has a dramatic effect on its speed and efficiency. Moreover, the proposed structure supports a zero-skipping scheme to reduce power consumption further. Our circuit-to-application co-simulation results demonstrate a comparable accuracy for our platform to the full-precision baseline on various object classification tasks while reaching an efficiency of <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula>3.48 TOp/s/W.

When arranged in a crossbar configuration, resistive memory devices can be used to execute Matrix-Vector Multiplications (MVMs), the most dominant operation of many Machine Learning (ML) algorithms, in constant time complexity. Nonetheless, when performing computations in the analog domain, novel challenges are introduced in terms of arithmetic precision and stochasticity, due to non-ideal circuit and device behaviour. Moreover, these non-idealities have a temporal dimension, resulting in a degrading application accuracy over time. Facing these challenges, we propose a novel framework, named <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LionHeart</i>, to obtain hybrid analog-digital mappings to execute Deep Learning (DL) inference workloads using heterogeneous accelerators. The accuracy-constrained mappings derived by <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LionHeart</i> showcase, across different Convolutional Neural Networks (CNNs) and one transformer-based network, high accuracy and potential for speedup. The results of the full system simulations highlight run-time reductions and energy efficiency gains that exceed 6×, with a user-defined accuracy threshold for a fully digital floating point implementation.

Encryption on large-scale memristor crossbars proves to be challenging due to the spatial and temporal fluctuations of the signals coming from numerous non-idealities. To address this, we utilize Hyperlock, a memristive vector-matrix multiplication accelerator employing hyperdimensional computing for encryption. We demonstrate that stochasticity generated on TiOx memristor crossbars with passive 0T1R arrangement can be decryptable under the appropriate training of a neural network. We present HyperXArray, an architecture for Hyperlock's encryption scheme, that is capable of weight regeneration, and analog/digital encryption without the need for high-resolution Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs). We demonstrate 100% decryption accuracy for digital encryption and show that HyperXArray is capable of encryption during analog to digital conversion that reduces the power consumption of ADC by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$50\times$</tex-math></inline-formula>. In digital encryption, we show that HyperXArray reduces energy consumption by up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10\times$</tex-math></inline-formula> and footprint by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10-100\times$</tex-math></inline-formula> compared to Field Programmable Gate Array (FPGA) implementations of Advanced Encryption Standard (AES), while maintaining the same level of throughput. Overall, HyperXArray demonstrates its capability to fill the niche for lightweight, noise-resilient encryption on edge with only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$0.1mm^{2}$</tex-math></inline-formula> footprint and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$60 pJ/bit$</tex-math></inline-formula> energy efficiency.